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advance data sheet december 2000 T8301 internet protocol telephone phone-on-a-chip ? ip solution dsp 1 introduction lucent technologies? phone-on-a-chip ip solution is a highly integrated set of ic chips that form the basic building blocks for an internet protocol tele- phone (ipt), residing on a local area network (lan). the ipt presently consists of two ics?the T8301 (ipt_dsp) and the t8302 (ipt_ arm *). the T8301 provides the audio processing engine for voice compression and decompression, speaker- phone echo cancellation, digital-to-analog and ana- log-to-digital converters, low-pass filters, and amplifiers to drive standard business telephone handsets and speakerphone hardware. the general-purpose processor chip t8302 controls system i/o (ethernet, usb, irda, etc.) and provides general telephone control features (led control, key- pad button scanning, lcd module interface, etc.). a block diagram of the T8301 can be found in figure 3 on page 8. since the dsp1627 is an integral part of the T8301, we will refer to the dsp1627 digital signal processor data sheet throughout this discussion. 1.1 features dsp1627 core with bit manipulation unit. dsp clock speeds up to 80 mhz. instruction rom, 32k x 16 (zero wait-state at 80 mhz). * arm is a registered trademark of advanced risc machines lim- ited. dual-port ram, 6k x 16 (zero wait-state at 80 mhz). internal sram, 16k x 16 (single wait-state at 80 mhz). 16-bit analog-to-digital converter. programmable gain amplifier on audio input. fixed gain differential microphone input. analog input sram buffer, 512 x 16. timed dma for analog input sram. two 16-bit digital-to-analog converters. independent simultaneous speaker and handset outputs. two integrated differential speaker driver outputs. two analog output sram buffers, 512 x 16 each. two timed dma outputs for simultaneous handset and speaker audio output. low-pass filtering on audio inputs and outputs. serial i/o interface. general-purpose timer counter. bit i/o interface. jtag test and debugging control. implementation in 0.35 m, 5 v silicon technology. packaged in 100-pin tqfp.
table of contents 2 lucent technologies inc. advance data sheet december 2000 phone-on-a-chip ip solution dsp T8301 internet protocol telephone contents page tables page 1 introduction .............................................................. 1 1.1 features ............................................................ 1 2 pin information ........................................................ 3 2.1 T8301 100-pin tqfp pin diagram ................... 3 2.2 pinout information ............................................. 4 3 overview .................................................................. 7 4 dsp1600 core ........................................................ 9 4.1 bit manipulation unit (bmu) .............................. 9 4.2 timer ................................................................. 9 4.3 clock pll control ............................................. 9 4.4 bit input/output (bio) ...................................... 10 4.5 serial input/output (sio) ................................. 10 4.6 interrupts and traps ........................................ 10 4.7 power management ........................................ 11 4.8 external memory interface (emi) .................... 11 4.9 T8301 memory mapping ................................. 11 4.10 y space memory map ................................... 15 5 audio input/output circuitry .................................. 17 5.1 analog audio input channels .......................... 17 5.2 programmable gain amplifier (pga) .............. 17 5.3 analog audio output channels ....................... 18 5.4 tone ringer ..................................................... 18 5.5 audio codec block .......................................... 20 5.6 audio codec control registers ....................... 21 6 dma input/output channels .................................. 23 6.1 dma operation ................................................ 23 6.2 dma registers ................................................ 23 7 hardware compander ........................................... 26 8 electrical specifications ......................................... 28 8.1 operating range specifications ...................... 28 8.2 analog and codec specifications .................... 28 8.3 crystal specification ........................................ 29 9 jtag and hardware development system (hds) ................................. 30 9.1 tmode control for jcs/boundary-scan operation ........................................................ 30 9.1.1 mode 7 operation (tmode = 7) ............ 30 9.1.2 mode 6 operation (tmode = 6) ............ 30 9.2 the principle of boundary-scan architecture ..................................................... 30 9.2.1 boundary-scan instruction register ................................ 32 figures page figure 1. T8301 tqfp pin diagram ........................... 3 figure 2. dsp/arm interface block diagram ............. 7 figure 3. T8301 block diagram .................................. 8 figure 4. crystal oscillator ......................................... 9 figure 5. audio codec block diagram ..................... 20 figure 6. hardware compander block diagram ....... 27 figure 7. boundary-scan architecture ..................... 31 table 1. pin description ............................................. 4 table 2. sio interface signals ..................................10 table 3. dsp1627 int0n and int1n ......................11 table 4. T8301 instruction/coefficient memory map ..............................................13 table 5. T8301 memory-mapped peripherals ..........14 table 6. data memory area: i/o, register, and memory ................................15 table 7. programmable gain amplifier maximum ....17 table 8. tone ringer control register (trc_reg) ......18 table 9. tone ringer amplitude control encoding ........................................19 table 10. tone ringer frequency encoding ............19 table 11. aioc_reg analog audio i/o control ...........21 table 12. audio codec clock control register (aclkc_reg) .....................22 table 13. audio clock encoding ..............................22 table 14. dma control register dmac_reg ..............24 table 15. dma starting address register setadr_reg ..................................24 table 16. dma transfer count register setcnt_reg ..................................24 table 17. dma address increment register adrinc_reg ..................................25 table 18. dma transfer decrement register cntdec_reg ................................................25 table 19. config_compander register ......................26 table 20. write_linear register .................................26 table 21. write_companded register .......................26 table 22. read_linear register .................................26 table 23. read_companded register .......................26 table 24. operating range specifications ...............28 table 25. ainan specifications ...............................28 table 26. aincp, aincn specifications ..................28 table 27. aouta specifications ..............................28 table 28. speaker#1, speaker#2 specifications ......29 table 29. digital low-pass filters specifications .....29 table 30. digital-to-analog converter specifications ...........................................29 table 31. analog-to-digital converter specifications ...........................................29 table 32. boundary-scan pin functions ..................32 table 33. debug mode ..............................................32 table 34. boundary-scan instruction register .........32 table 35. boundary-scan register description .......33
lucent technologies inc. 3 advance data sheet december 2000 T8301 internet protocol telephone phone-on-a-chip ip solution dsp 2 pin information 2.1 T8301 100-pin tqfp pin diagram 5-8211(f) figure 1. T8301 tqfp pin diagram v dd bio0 bio1 bio2 bio3 int0n int1n stopn di1 v ss v dd do1 sync iold iock v ss v dd pll cki1 cki2 v ss pll a15 a14 a13 a12 v ss aincp aincn ainan v ss gb v dd gb sti1 sto1 stck ck8khz v dd v ss d0 d1 d2 d3 d4 d5 d6 d7 v dd v ss d8 d9 d10 d11 v ss cko ck2mhz tdi tms tck tdo resetn tmoden2 tmoden1 tmoden0 trstn v dd gb v ss gb sv dd spkdrv2a spkdrv2b sv ss sv ss spkdrv1b spkdrv1a sv dd v dd a aouta gnda v dd a11 a10 a9 a8 a7 a6 a5 a4 v ss v dd a3 a2 a1 a0 i_csn m_csn x_csn rwn v ss v dd d15 d14 d13 d12 1 10 20 30 40 50 60 70 80 90 100 T8301 (100-pin tqfp)
4 lucent technologies inc. phone-on-a-chip ip solution dsp T8301 internet protocol telephone advance data sheet december 2000 2 pin information (continued) 2.2 pinout information in the following table, reference 1 refers to sections in the T8301 data sheet (this data sheet) and reference 2 refers to sections in the dsp1627 data sheet. table 1. pin description pin # name description reference 1 reference 2 1v dd ??? 2 bio0 bit i/o 0 4.4 4.9 3 bio1 bit i/o 1 4.4 4.9 4 bio2 bit i/o 2 4.4 4.9 5 bio3 bit i/o 3 4.4 4.9 6 int0n dsp interrupt 0, active -low 4.6 4.3 7 int1n dsp interrupt 1, active -low 4.6 4.3 8 stopn controls the internal processor clock, active -ow ? 4.13 9 di1 serial input/output unit (sio) data in 4.5 4.7 10 v ss ??? 11 v dd ??? 12 do1 serial input/output unit (sio) data out 4.5 4.7 13 sync serial input/output unit (sio) sync 4.5 4.7 14 iold serial input/output unit (sio) input load/output load 4.5 4.7 15 iock serial input/output unit (sio) input clock/output clock 4.5 4.7 16 v ss ??? 17 v dd pll osc and pll v dd ?? 18 cki1 xtl1 input/cmos clock 4.3 4.12 19 cki2 xtl2 input/cmos clock 4.3 4.12 20 v ss pll osc and pll v ss ?? 21 a15 emi address bus 15 4.9 ? 22 a14 emi address bus 14 4.9 4.5, 6.2 23 a13 emi address bus 13 4.9 4.5, 6.2 24 a12 emi address bus 12 4.9 4.5, 6.2 25 v ss ??? 26 v dd ??? 27 a11 emi address bus 11 4.9 4.5, 6.2 28 a10 emi address bus 10 4.9 4.5, 6.2 29 a9 emi address bus 9 4.9 4.5, 6.2 30 a8 emi address bus 8 4.9 4.5, 6.2 31 a7 emi address bus 7 4.9 4.5, 6.2 32 a6 emi address bus 6 4.9 4.5, 6.2 33 a5 emi address bus 5 4.9 4.5, 6.2 34 a4 emi address bus 4 4.9 4.5, 6.2 35 v ss ??? 36 v dd ??? 37 a3 emi address bus 3 4.9 4.5, 6.2
lucent technologies inc. 5 advance data sheet december 2000 phone-on-a-chip ip solution dsp T8301 internet protocol telephone 2 pin information (continued) 38 a2 emi address bus 2 4.9 4.5, 6.2 39 a1 emi address bus 1 4.9 4.5, 6.2 40 a0 emi address bus 0 4.9 4.5, 6.2 41 i_csn arm interrupt chip select, active-low 4.10, table 6 ? 42 m_csn arm memory chip select, active-low 4.10, table 6 ? 43 x_csn external memory chip select, active-low 4.10, table 6 ? 44 rwn read/write, active-low ? 4.5, 6.2 45 v ss ??? 46 v dd ??? 47 d15 emi data bus 15 3 4.5, 6.2 48 d14 emi data bus 14 3 4.5, 6.2 49 d13 emi data bus 13 3 4.5, 6.2 50 d12 emi data bus 12 3 4.5, 6.2 51 d11 emi data bus 11 3 4.5, 6.2 52 d10 emi data bus 10 3 4.5, 6.2 53 d9 emi data bus 9 3 4.5, 6.2 54 d8 emi data bus 8 3 4.5, 6.2 55 v ss ??? 56 v dd ??? 57 d7 emi data bus 7 3 4.5, 6.2 58 d6 emi data bus 6 3 4.5, 6.2 59 d5 emi data bus 5 3 4.5, 6.2 60 d4 emi data bus 4 3 4.5, 6.2 61 d3 emi data bus 3 3 4.5, 6.2 62 d2 emi data bus 2 3 4.5, 6.2 63 d1 emi data bus 1 3 4.5, 6.2 64 d0 emi data bus 0 3 4.5, 6.2 65 v ss ??? 66 v dd ??? 67 ck8khz test clock 9.1 ? 68 stck serial test clock* ? ? 69 sto1 serial test out 1* ? ? 70 sti1 serial test in 1* ? ? 71 v dd gb ? ? ? 72 v ss gb ? ? ? 73 ainan (handset) single-ended microphone input 5.1 ? 74 aincn (speakerphone) microphone differential input negative 5.1 ? 75 aincp (speakerphone) microphone differential input positive 5.1 ? 76 gnda ? ? ? 77 aouta (handset) single-ended speaker output 5.3 ? 78 v dd a? ? ? * leave open, this is for test purposes only. table 1. pin description (continued) pin # name description reference 1 reference 2
6 lucent technologies inc. phone-on-a-chip ip solution dsp T8301 internet protocol telephone advance data sheet december 2000 2 pin information (continued) 79 sv dd ??? 80 spkdrv1a (speakerphone) speaker#1 differential output driver a 5.3 ? 81 spkdrv1b (speakerphone) speaker#1 differential output driver b 5.3 ? 82 sv ss ??? 83 sv ss ??? 84 spkdrv2b (speakerphone) speaker#2 differential output driver b 5.3 ? 85 spkdrv2a (speakerphone) speaker#2 differential output driver a 5.3 ? 86 sv dd ??? 87 v ss gb ? ? ? 88 v dd gb ? ? ? 89 trstn jtag test reset input, active-low 9.2 ? 90 tmoden0 test mode 0 9.1 ? 91 tmoden1 test mode 1 9.1 ? 92 tmoden2 test mode 2 9.1 ? 93 resetn chip reset, active-low ? 10.2 94 tdo jtag test data out 9.2 6.6 95 tck jtag test clock 9.2 6.6 96 tms jtag mode select 9.2 6.6 97 tdi jtag test data in 9.2 6.6 98 ck2mhz clock out 9.1 ? 99 cko dsp clock out 9.1 4.12 100 v ss ??? table 1. pin description (continued) pin # name description reference 1 reference 2
lucent technologies inc. 7 advance data sheet december 2000 T8301 internet protocol telephone phone-on-a-chip ip solution dsp 3 overview the T8301 (dsp) interfaces with the t8302 ( arm ) to form the basic building blocks for an internet protocol tele- phone (ipt), residing on a local area network (lan); see figure 2. at the heart of the T8301 integrated circuit is the lucent technologies microelectronics group dsp1627 digital sig- nal processor core. the dsp1627?s high-performance (80 mips) and single-cycle multiply accumulate instruction provide excellent support for execution of voice compression/decompression and echo cancellation algorithms. the dsp1627 core and the analog audio circuitry included on the T8301 ic provide a low-cost silicon solution for the ip exchange telephone?s audio requirements. a block diagram of the T8301 integrated circuit is shown in figure 3. the dsp1627 core contains the dsp1600 core processor, bit manipulation unit (bmu), dual-port ram (dpram), instruction/coefficient rom (irom), bit i/o (bio), serial i/o (sio), timer, clock pll control, vectored interrupts and traps, power management, external memory interface (emi) with wait-state control, and a jtag interface with inte- gral hardware development system support. the dsp1627 peripherals communicate with the dsp1627 core through the (d-idb bus), which is 16 bits wide. the dsp1627 core?s harvard architecture allows efficient memory utilization by supporting separate instruction (xdb, xab) and data (ydb, yab) address spaces. the dual-port ram (dpram) is connected to both address and data buses xdb, ydb, xab, and yab, while the instruction rom is only connected to the xdb and xab memory bus. the external memory interface provides a mechanism to access i/o devices and memories that are not part of the core dsp1627 hardware. for a complete description of the dsp1627 core and its peripherals, refer to the dsp1627 digital signal processor data sheet. a brief description of the functionality of the dsp1627 is provided in the following section. where nec- essary, comments are made which reflect differences between the operation of the dsp1627 and the T8301. please refer to the dsp1627 data sheet for further explanation. figure 2. dsp/ arm interface block diagram resetn dsp_int0n dsp_mcsn dsp_icsn dsp_rwn dsp_a0?dsp_a11 dsp_d0?dsp_d15 resetn int0n m_cs i_csn rwn a0?a11 d0?d15 x_csn trstn tdo tdi tc tms int1n bio0 bio1 bio2 bio3 stck sto1 sti1 tmoden0 tmoden1 tmoden2 do1 di1 iock iold sync spkdrv1a spkdrv1b aincp aincn spkdrv2a spkdrv2b ainan aouta cki1 cki2 cko ck8khz ck2mhz dsp arm boundary scan and/or jtag optional (memory) device on 12k y data bus test mode select pins ate analog test pins optional bit input output optional external serial codec speakerphone speaker and mic handset speaker and mic headset speaker x = leave open if unused 12.288 mhz clock source optional clock resources
8 lucent technologies inc. phone-on-a-chip ip solution dsp T8301 internet protocol telephone advance data sheet december 2000 3 overview (continued) 5-8210 (f) figure 3. T8301 block diagram dma output dmas counter address output dmah counter address input dma counter address dmac reg trc_reg tone ringer aioc audio codec block act1 act2 audio clock generator aclkc sout sram buffer 512 x 16 aouta sram buffer 512 x 16 ain sram buffer 512 x 16 address decode pga 0?21 db in 3 db ?or? internal sram 16k x 16 sio sdx(out) srta tdms sdx(in) sioc saddx timer timerc timer 0 bio sbit cbit ydb yab data bus dsp 1600 core xab xdb instruction/ coefficient bus i n t e r r d-idb bmu aa0 aa1 ar1 ar2 ar0 ar3 u p t dpram 6k x 16 irom 32k x 16 external memory interface ioc mwait jtag jtag jcon id bypass breakpoint trace hds clock/pll pllc & power powerc dsp1627 core + erom eramhi i/o eramlo rwn a[15:0] d[15:0] stck sto1 sti1 spkdrv1a spkdrv2a spkdrv2b aouta aincp aincn ainan tmoden0 tmoden1 tmoden2 cko resetn stopn ck8khz ck2mhz tdo tdi tck tms int1n int0n d(15:0) a(15:0) rwn i_csn m_csn x_csn iold iock sync do1 di1 bio[3:0] cki2 cki1 spkdrv1b or dmaint steps trstn 30 db + ? 12 db 2.5 vp-p 12 db 1.5 db
lucent technologies inc. 9 advance data sheet december 2000 T8301 internet protocol telephone phone-on-a-chip ip solution dsp 4 dsp1600 core the discussions in this section pertain to circuitry that is inside of the dotted outline in figure 3. for additional resources, please refer to the dsp1627 digital signal processor data sheet. the dsp1600 core includes a data arithmetic unit, memory addressing units, cache, and a control section. in com- bination, these elements support a diverse instruction set for implementing users? algorithms. 4.1 bit manipulation unit (bmu) the bmu provides extensive bit manipulation capabilities that increase the dsp1627?s efficiency in processing data. 4.2 timer the dsp1627 core contains a programmable interrupt timer that can be configured to count over a wide range of frequencies. this timer provides flexibility in timing events. 4.3 clock pll control the dsp1627 powers up with the input clock ( cki1/cki2 in the T8301 ic) as the source for the processor clock. an on-chip clock synthesizer (pll) can also be used to generate the system clock for the dsp1627, which will run at a frequency multiple of the input clock. the clock synthesizer is deselected and powered down on reset. for low- power operation, an internally generated slow clock can be used to drive the dsp1627. if both the clock synthe- sizer and the internally generated slow clock are selected, the slow clock will drive the dsp1627; however, the syn- thesizer will continue to run. the clock synthesizer and other programmable clock sources are discussed in the dsp1627 data sheet. the use of these programmable clock sources for power management is also discussed in the dsp1627 data sheet. board designers should refer to the section on v dda and v ssa connections in the data sheet for specific connection and filtering requirements on the clock synthesizer power and ground leads. note: the 12,288 khz is required as shown. variations from this crystal frequency will cause detrimental effects to speech qual ity. figure 4. crystal oscillator oscillator to pll 768 16 khz to codecs cki1 cki2 load capacitor load capacitor 12,288 khz crystal
10 lucent technologies inc. phone-on-a-chip ip solution dsp T8301 internet protocol telephone advance data sheet december 2000 4 dsp1600 core (continued) 4.4 bit input/output (bio) the bio provides convenient and efficient monitoring and control of four individually configurable pins. when con- figured as outputs, the pins can be individually set, cleared, or toggled. when configured as inputs, individual pins or combinations of pins can be tested for patterns. flags returned by the bio mesh seamlessly with conditional instructions. although the dsp1627 has eight bios available, the T8301 makes the four low-order bios available on pins. 4.5 serial input/output (sio) the serial i/o interface (sio) of the T8301 closely follows the serial interface of the dsp1627. the T8301 multi- plexes certain dsp1627 sio pins and eliminates some others to reduce the total pin count. hysteresis input buffers are used for the sio clocks on this device ( iold, iock , and sync ). the table below shows the signals that com- prise the T8301 sio interface. *iold is comprised of the ild1 and the old1 signals from the dsp1627 core tied together. by default, the iold signal is an input, which cor- responds to the two dsp1627 load signals configured as passive. however, input load 1 ( ild1 ) may be configured as active, which then con- figures the iold signal as an output. in this case, the internal input load 1 ( ild1 ) drives the output load signal ( old1 .) iock is analogous to iold . input clock 1 can be configured as an output, which would then drive iock and ock1 . if the pll is enabled, care should be taken if using iock as an output since there may be an unacceptable amount of jitter on the clock. the sync signal is intended to provide synchronization of the serial bus with an external 8 khz frame clock. when sync is configured as an input and asserted, the sio load counter is reset and iold is asserted (if configured as an output). for typical applications, the sio will be configured to have sync and iock as inputs and iold as an output (from the dsp1627 core). in this configuration, there are thirty-two 8-bit (sixteen 16-bit) time slots for each sio channel and sync provides the 8 khz sio frame timing. the timing relationship for this configuration can be found in the dsp1627 data sheet. 4.6 interrupts and traps the dsp1627 supports prioritized, vectored interrupts, and a trap. there are eight internal hardware sources for program interrupt and two external interrupt pins. additionally, there is a trap signal from the hardware development system (hds). each of the sources has a unique vector address and priority assigned to it. refer to the dsp1627 data sheet for more information. the use of the two external dsp1627 core interrupts is shown in table 3 and in figure 2. table 2. sio interface signals symbol type function di1 i serial data in 1. do1 o serial data out 1. iold* i/o input/output load for sio 1. iock i/o input/output clock for sio 1. sync i/o sync for sio 1 and 2.
lucent technologies inc. 11 advance data sheet december 2000 phone-on-a-chip ip solution dsp T8301 internet protocol telephone 4 dsp1600 core (continued) int0n is dedicated to the arm dcc interrupts in the dsp?s mask rom. int1n is internally ored with the dma interrupt. the dsp?s mask rom for int1 is dedicated to dma servicing. it is recommended that int1n float (inter- nal pull up on pin). 4.7 power management there are three different power management control mechanisms: the power control register ( powerc ), the stop pin ( stopn ), and the await bit in the alf register . refer to the dsp1627 data sheet for more information concerning these registers and their usage. 4.8 external memory interface (emi) the T8301 external memory interface is used to access the non-dsp1627 core features provided in the T8301 integrated circuit. the external memory interface is also used to access off-chip resources such as the interproces- sor communication memories contained in the ipt_arm integrated circuit. the T8301 external memory interface requires one wait-state to access on-chip resources and two wait-states to access 15 ns or faster off-chip resources when operating at 80 mhz. 4.9 T8301 memory mapping the T8301 contains various types of memory modules, all with varying characteristics, aside from their memory map location. as a harvard architecture, the device has two address/data buses; these are referred to as x and y. the x system is used for program instructions and data, and the y system is typically for data and memory mapped i/o. memory is 16 bits wide. the dsp1627 can vary the x bus memory map based on the logic levels on two signals: exm and lowpr . how- ever, the T8301 has exm tied low internally, reducing the possibilities to two. the two memory maps are the dsp1627?s map1 and map3. lowpr is software controllable. when using the dsp1627 software tools (with jcs i.e., jtag communications system) the tools will configure lowpr automatically based upon the link time compile options of the .if file. map1 is the default map. the basic difference of the two maps is the type of memory at the reset vector (0x0000). map1 has rom at 0x0000, and map3 has ram at 0x0000. the y map is fixed. the T8301 is a masked rom-coded device and contains no flash memory. map 1 is typically used for production, and map 3 is typically used for code development. when used in conjunction to the t8302 arm embedded proces- sor, the arm will be required to pass all code and data to the dsp's ram at power up reset. a hardware/software protocol must be instituted to allow the arm to successfully load code into the dsp. note: all x memory references are map 3. internal rom, irom?32k x 16: ? responds only to the x data bus, the x memory location is 0x4000?0xbfff. this block will operate with zero wait-states. table 3. dsp1627 int0n and int1n interrupt function interrupt priority int1n interrupt from dma block or external interrupt 1, active-low. 4 (higher) int0n external interrupt input 0, active-low. 2
12 lucent technologies inc. phone-on-a-chip ip solution dsp T8301 internet protocol telephone advance data sheet december 2000 4 dsp1600 core (continued) dual-port (core) ram, dpram?6k x 16: ? this block is a true dual-port memory and is accessible simultaneously by both the x and y bus system. two locations can be either read or written in the same instruction execution. this memory block resides at loca- tions 0x0000?0x17ff on both the x and y maps. this block will operate with zero wait states. the dpram contains 6k x 16-bit words of zero wait-state memory, which is organized into six banks of 1k x 16-bit words. each bank has separate ports to the instruction/coefficient and data memory spaces. dual accesses to both memory spaces in separate banks incur no wait-states; however, accesses to the same bank from both spaces will add one wait-state to the total access time. internal sram, isram?16k x 16: ? although this is a dual-port ram, there is only one bus system to the ram itself. the x and y bus is multi- plexed before the ram and is actually addressed via the external memory interface (emi). two locations can be either read or written in the same instruction execution, but will require two clock cycles. the x memory location is at 0xc000?0xffff and the y memory location is at 0x8000?0xbfff, and also at 0xc000? 0xffff. (referred to as mirrored. a write to 0x8000 on the y map will also write to 0xc000). there is only one block of 16k; however, it appears twice on the y map. there is one wait-state required for both the x and y bus to access this ram . external sram, xsram?12k x 16: ? responds only to the y data bus. the T8301 generates a chip select called x_csn (active-low), pin 43. it uses the emi to generate the address and data. there is one wait-state required for both the x and y bus to access this ram .
lucent technologies inc. 13 advance data sheet december 2000 phone-on-a-chip ip solution dsp T8301 internet protocol telephone 4 dsp1600 core (continued) table 4. T8301 instruction/coefficient memory map address x map1 x map3 address y map 0x0000 0x0000 0x0800 dual-port ram 6k 0x0800 dual-port ram 6k 0x1000 (dpram) 0x1000 (dpram) 0x1800 0x1800 0x2000 internal rom 32k 0x2000 0x2800 (irom) reserved 10k 0x2800 reserved 10k 0x3000 0x3000 0x3800 0x3800 0x4000 (instructions 0x4000 i/o and eramlo (see table 5.) 0x4800 and constants) 0x4800 eramlo (see table 5.) 0x5000 0x5000 0x5800 0x5800 eramlo external chip select 0x6000 internal rom 32k 0x6000 x_csn (external sram) 12k 0x6800 (irom) 0x6800 0x7000 0x7000 0x7800 0x7800 0x8000 (instructions 0x8000 0x8800 and constants) 0x8800 0x9000 internal sram 16k 0x9000 internal sram 16k 0x9800 (isram) 0x9800 (1k?16k block mirrored) 0xa000 0xa000 (isram) 0xa800 0xa800 0xb000 0xb000 0xb800 0xb800 0xc000 0xc000 0xc800 dual-port ram 6k 0xc800 0xd000 (dpram) internal sram 16k 0xd000 internal sram 16k 0xd800 (isram) 0xd800 (1k?16k block mirrored) 0xe000 0xe000 (isram) 0xe800 reserved 10k 0xe800 0xf000 0xf000 0xf800 0xf800
14 lucent technologies inc. phone-on-a-chip ip solution dsp T8301 internet protocol telephone advance data sheet december 2000 4 dsp1600 core (continued) table 5. T8301 memory-mapped peripherals address y map 0x4000 analog i/o devices 0x4100 (i_csn) dcc control interface 0x4200 audio input, sram (512) read only 0x4300 0x4400 handset audio output, sram (512) write only 0x4500 0x4600 speaker audio output, sram (512) write only 0x4700 0x4800 m_csn 0x4900 arm-to-dsp 0x4a00 buffer (1k) 0x4b00 0x4c00 m_csn 0x4d00 dsp-to-arm 0x4e00 buffer (1k) 0x4f00
lucent technologies inc. 15 advance data sheet december 2000 phone-on-a-chip ip solution dsp T8301 internet protocol telephone 4 dsp1600 core (continued) 4.10 y space memory map the table below shows the y space memory map. this is the area can be addressed via the dsp1627?s r0, r1, r2, and r3 registers, and also by direct (y-based) addressing. table 6. data memory area: i/o, register, and memory address r/w dsp cs function description size (words) 0x0:0x17ff r/w internal internal ram ? 6k 0x4000 r/w i/o aioc_reg analog audio i/o control register, see table 11. 1 0x4001 r/w i/o act1_reg audio codec test register 1. 1 0x4002 r/w i/o act2_reg audio codec test register 2. 1 0x4003 r/w i/o aclkc_reg audio codec clock control register, see table 12. 1 0x4008 r/w i/o trc_reg tone ringer control register, see table 8. 1 0x4010 r/w i/o dmac_reg dma control register, see table 14. 1 0x4014 r/w i/o ainsetadr_reg audio in dma starting address register, see table 15. 1 0x4015 r/w i/o ainsetcnt_reg audio in dma transfer count registers, see table 16. 1 0x4016 r/w i/o ainadrinc_reg audio in dma address increment registers, see table 17. 1 0x4017 r/w i/o aincntdec_reg audio in dma transfer count decrement regis- ter, see table 18. 1 0x4018 r/w i/o hndsetadr_reg handset dma starting address register, see table 15. 1 0x4019 r/w i/o hndsetcnt_reg handset dma transfer count register, see table 16. 1 0x401a r/w i/o hndadrinc_reg handset dma address increment register, (see table 17). 1 ox401b r/w i/o hndcntdec_reg handset dma transfer count decrement register, see table 18. 1 0x401c r/w i/o spksetadr_reg speaker dma starting address register, see table 15. 1 0x401d r/w i/o spksetcnt_reg speaker dma transfer count register, see table 16. 1 0x401e r/w i/o spkadrinc_reg speaker dma address increment register, see table 17. 1 0x401f r/w i/o spkcntdec_reg speaker dma transfer count decrement register, see table 18. 1 0x4040 r/w i/o config_compander compander configuration register, see table 19. 1 0x4041 w i/o write_companded write companded value register, see table 21. 1 0x4041 r i/o read_linear read linear value register, see table 22. 1 0x4042 w i/o write_linear write linear value register, see table 20. 1
16 lucent technologies inc. phone-on-a-chip ip solution dsp T8301 internet protocol telephone advance data sheet december 2000 4 dsp1600 core (continued) address r/w dsp cs function description size (words) 0x4042 r i/o read_companded read companded value register, see table 23. 1 0x4100:0x4107 r/w eramlo i_csn external chip select to access token registers. 8 0x4108:x410b r/w eramlo i_csn external chip select to access arm interrupt register. 4 0x410c:0x410f r/w eramlo i_csn external chip select to access dsp interrupt register. 4 0x4110:0x41ff r/w eramlo i_csn reserved. 240 0x4200:0x43ff r eramlo ain sram audio input sram buffer. 512 0x4400:0x45ff w eramlo aouta sram handset audio out sram buffer. 512 0x4600:0x47ff w eramlo sout sram speaker audio out sram buffer. 512 0x4800:0x4bff r eramlo m_csn external chip select to access arm to dsp ram (in the t8302 ipt_arm chip). 1k 0x4c00:0x4fff w eramlo m_csn external chip select to access dsp to arm ram (in the t8302 ipt_arm chip). 1k 0x5000:0x7fff r/w eramlo x_csn external spare chip select. 12k 0x8000:0xbfff r/w eramhi isram internal sram. 16k table 6. data memory area: i/o, register, and memory (continued)
lucent technologies inc. 17 advance data sheet december 2000 T8301 internet protocol telephone phone-on-a-chip ip solution dsp 5 audio input/output circuitry the discussions in this section pertain to circuitry that is outside of the dotted outline in figure 3 on page 8. 5.1 analog audio input channels the T8301 contains analog interfaces designed to support a 150 ? handset as well as an additional microphone and two speakers. the T8301 integrated circuit contains two audio analog inputs. there is a single-ended input ( ainan ) to be con- nected to a standard business telephone handset receiver. there is a differential input ( aincp , aincn ) to be con- nected to a microphone. this provides the T8301 with the input circuitry to implement a speakerphone. the differential input is directly connected to a 30 db amplifier. the input select multiplexer routes ainan or the output of the fixed 30 db amplifier to a programmable gain amplifier (pga). the programmable gain amplifier is adjustable from 0 db to 21 db in 3 db steps. the signal output from the programmable gain amplifier is then routed to the audio codec block to be digitized. each of the input signals ainan , aincp , and aincn are ac-coupled to their T8301 inputs by a 0.2 f capacitor. the maximum signal input to the codec is 2.5 vp-p. if the user sets the amplification to a value that would produce a larger signal than 2.5 vp-p, the audio codec will saturate and clip the input waveform. the maximum input signal from the handset or from the microphone that can be supported for each gain setting is listed in table 7. since the microphone amplifier has a maximum specified signal of 40 mv, the maximum micro- phone input is not supported for pga settings of 0 db and 3 db. 5.2 programmable gain amplifier (pga) the programmable gain amplifier is using the pgas[2:0] bits of the aioc_reg (see table 11 on page 21). the set- table gain values and their tolerances are shown below as well as the maximum allowed input signal voltage from each of the input signals. inputs greater than these values will saturate the input codec and produce clipped wave- forms. table 7. programmable gain amplifier maximum bit code gain max input signal ainan aincn, aincp 000 0 db 0.5 db 2.500 vp-p not supported 001 3 db 0.5 db 1.770 vp-p not supported 010 6 db 0.5 db 1.250 vp-p 40.0 mvp-p 011 9 db 0.5 db 0.844 vp-p 28.3 mvp-p 100 12 db 0.5 db 0.625 vp-p 20.0 mvp-p 101 15 db 1.0 db 0.442 vp-p 14.2 mvp-p 110 18 db 1.0 db 0.313 vp-p 10.0 mvp-p 111 21 db 1.5 db 0.221 vp-p 7.1 mvp-p
18 lucent technologies inc. phone-on-a-chip ip solution dsp T8301 internet protocol telephone advance data sheet december 2000 5 audio input/output circuitry (continued) 5.3 analog audio output channels the T8301 contains two independent analog audio output ports. there is a single-ended output signal, aouta , that can be connected to the speaker of a standard 150 ? business telephone handset or to a differential speaker driver spkdrv2 . differential speaker driver, spkdrv1 , can be set up to ring the phone by adding in the tone ringer output into its audio path. differential speaker driver output pins ( spkdrv1a , spkdrv1b and spkdrv2a , spkdrv2b ) should be con- nected to 45 ? speakers. both outputs receive their analog signals from the audio codec block, which converts the two digital input streams to analog signals. the maximum signal from the codec is 2.5 vp-p. the aouta signal has a maximum 2.5 vp-p signal swing. it should maintain a midlevel bias to prevent load noises when the driver is re-enabled. the speaker outputs ( spkdrv1a , spkdrv1b and spkdrv2a , spkdrv2b ) each have 3 vp-p signal swing. since these outputs are of opposite polarity, the differential signal output is 6 vp-p. this is a 6 db effective amplification of the codec output signal. the signals should be biased such that, when power is re-enabled, no audible noises occur. the differential speaker output driver does not have to produce a full 6 vp-p signal without distortion. signals above 5 vp-p measured from spkdrvxa to spkdrvxb may be in the nonlinear range of the differential amplifier and exhibit a flattening or clipping characteristic at the output. aouta is ac coupled to the handset speaker using a 2 f capacitor. the speaker driver outputs ( spkdrv1a, spkdrv1b and spkdrv2a , spkdrv2b ) are direct coupled to 45 ? speakers. 5.4 tone ringer the T8301 analog circuitry contains a tone ringer generator. when this circuit is powered up and enabled, the ring- ing tone output is added to the current analog speaker signal and output through the differential speaker driver. custom tones may be generated by modifying the T8301 firmware. table 8. tone ringer control register (trc_reg) tone ringer control register (trc_reg) address (0x4008) bit # 15:13 12 11:8 7:0 name rsvd tr_en tr_ac[3:0] tr_fc[7:0] bit # name description 15:13 rsvd reserved. 12 tr_en tone ringer output enable. if 1, the tone ringer?s output is added into the speaker output path. if 0, the tone ringer?s output is disconnected from the speaker output path. 11:8 tr_ac[3:0] tone ringer amplitude control, see table 9. 7:0 tr_fc[7:0] tone ringer frequency control, see table 10. (the tone ringer frequencies are listed in hex format).
lucent technologies inc. 19 advance data sheet december 2000 phone-on-a-chip ip solution dsp T8301 internet protocol telephone 5 audio input/output circuitry (continued) table 9. tone ringer amplitude control encoding bit# tr_ac[3:0] volts out (p-p) db relative to maximum level tolerance (db from nominal) 0 0 0 0 silent dc to midvoltage reference not applicable 0 0 0 1 0.023 v ?40.60 0.75 0 0 1 0 0.032 v ?37.74 0.75 0 0 1 1 0.045 v ?34.88 0.75 0 1 0 0 0.063 v ?32.02 0.50 0 1 0 1 0.087 v ?29.16 0.50 0 1 1 0 0.120 v ?26.30 0.50 0 1 1 1 0.170 v ?23.44 0.25 1 0 0 0 0.230 v ?20.58 0.25 1 0 0 1 0.330 v ?17.72 0.25 1 0 1 0 0.460 v ?14.86 0.25 1 0 1 1 0.620 v ?12.00 0.25 1 1 0 0 0.880 v ?9.00 0.25 1 1 0 1 1.250 v ?6.00 0.25 1 1 1 0 1.770 v ?3.00 0.25 1 1 1 1 2.500 v 0 not applicable table 10. tone ringer frequency encoding tone ringer frequency encoding hz hex hz hex hz hex hz hex hz hex hz hex 24,000 3f 1,067 1d 545.5 35 366.4 6c 277.5 2a 223.3 c5 16,000 1f 1,043 0e 539.3 9a 363.6 36 275.9 95 222.2 62 12,000 0f 1,021 07 533.3 4d 360.9 1b 274.3 ca 221.2 31 9,600 87 1,000 03 527.5 a6 358.2 8d 272.7 e5 220.2 18 8,000 43 979.5 81 521.7 d3 355.5 c6 271.2 72 219.2 0c 6,857 a1 960.0 c0 516.1 69 352.9 e3 269.7 b9 218.2 06 6,000 d0 941.2 60 510.6 34 350.4 f1 268.2 dc 217.2 83 5,333 e8 923.1 30 505.3 1a 347.8 78 266.7 ee 216.2 c1 4,800 f4 905.6 98 500.0 0d 345.3 3c 265.2 77 215.3 e0 4,364 7a 888.9 4c 494.8 86 342.8 9e 263.7 bb 214.3 70 4,000 3d 872.7 26 489.8 c3 340.4 cf 262.3 dd 213.3 b8 3,692 1e 857.1 93 484.9 e1 338.0 e7 260.9 6e 212.4 5c 3,429 8f 842.1 49 480.0 f0 335.7 73 259.5 37 211.5 ae 3,200 c7 827.6 24 475.2 f8 333.3 39 258.1 9b 210.5 57 3,000 63 813.6 92 470.6 7c 331.0 9c 256.7 cd 209.6 ab 2,824 b1 800.0 c9 466.0 be 328.8 ce 255.3 e6 208.7 55 2,667 58 786.9 64 461.5 df 326.5 67 253.9 f3 207.8 aa 2,526 2c 774.2 b2 457.1 6f 324.3 33 252.6 79 206.9 d5 2,400 16 761.9 d9 452.8 b7 322.1 19 251.3 bc 206.0 ea 2,286 0b 750.0 ec 448.6 db 320.0 8c 250.0 de 205.1 f5 2,182 05 738.5 76 444.4 ed 317.9 46 248.7 ef 204.3 fa
20 lucent technologies inc. phone-on-a-chip ip solution dsp T8301 internet protocol telephone advance data sheet december 2000 5 audio input/output circuitry (continued) 5.5 audio codec block the T8301 contains a 16-bit analog-to-digital converter and two 16-bit digital-to-audio converters. these convert- ers each contain appropriate antialiasing or smoothing filters. a block diagram of the audio codec block is shown below. . 5-8212 (f) figure 5. audio codec block diagram 2,087 02 727.3 3b 440.4 f6 315.8 a3 247.4 f7 203.4 7d 2,000 01 716.4 9d 436.4 7b 313.7 d1 246.2 fb 202.5 3e 1,920 80 705.9 4e 432.4 bd 311.7 68 244.9 fd 201.7 9f 1,846 40 695.7 27 428.6 5e 309.7 b4 243.7 7e 200.8 4f 1,778 20 685.7 13 424.8 af 307.7 5a 242.4 bf 200.0 a7 1,714 10 676.1 09 421.1 d7 305.7 2d 241.2 5f 199.2 53 1,655 88 666.7 04 417.4 eb 303.8 96 240.0 2f 198.3 29 1,600 c4 657.5 82 413.8 75 301.9 4b 238.8 97 197.5 14 1,548 e2 648.6 41 410.3 ba 300.0 25 237.6 cb 196.7 0a 1,500 71 640.0 a0 406.8 5d 298.1 12 236.5 65 195.9 85 1,455 38 631.6 50 403.4 2e 296.3 89 235.3 32 195.1 42 1,412 1c 623.4 a8 400.0 17 294.5 44 234.1 99 194.3 21 1,371 8e 615.4 d4 396.7 8b 292.7 a2 233.0 cc 193.5 90 1,333 47 607.6 6a 393.4 45 290.9 51 231.9 66 192.8 c8 1,297 23 600.0 b5 390.2 22 289.2 28 230.8 b3 192.0 e4 1,263 91 592.6 da 387.1 11 287.4 94 229.7 59 191.2 f2 1,231 48 585.4 6d 384.0 08 285.7 4a 228.6 ac 190.5 f9 1,200 a4 578.3 b6 380.9 84 284.0 a5 227.5 56 189.7 fc 1,171 d2 571.4 5b 377.9 c2 282.4 52 226.4 2b 189.0 fe 1,143 e9 564.7 ad 375.0 61 280.7 a9 225.4 15 188.2 ff 1,116 74 558.2 d6 372.1 b0 279.1 54 224.3 8a ? ? 1,0913a551.76b369.2d8?????? table 10. tone ringer frequency encoding (continued) tone ringer frequency encoding hz hex hz hex hz hex hz hex hz hex hz hex sdm x 16 rcv intrp x 4 rcv lpf x 2 sdm x 16 rcv intrp x 4 rcv lpf x 2 1 mbit/s 64 ks/s 16 ks/s 8 ks/s sinc3 decm / 64 xmt bpf / 2 1 mbit/s 16 ks/s 8 ks/s 16 amux dmux from to from dac 16-bit dac 16-bit adc 16-bit low-pass rc filter low-pass rc filter low-pass rc filter to speaker driver to handset output from ain mux or speaker driver 2 dmas dmah dmain
lucent technologies inc. 21 advance data sheet december 2000 phone-on-a-chip ip solution dsp T8301 internet protocol telephone 5 audio input/output circuitry (continued) 5.6 audio codec control registers the analog audio input and output control register ( aioc_reg ) is used to select the active and enabled inputs and outputs. through this register the input and output channels can also have the clocks shut down to conserve power. table 11. aioc_reg analog audio i/o control analog audio input and output control register (aioc_reg): address (0x4000) bit # 15 14 13 12 11 10 9:8 name mpwrd spkfb hndfb ainfb spk2en ole rsvd bit # 7 65 4 3 2 1:0 name rsvd pgas(2) pgas(1) pgas (0) spken aoutaen ainss[1:0] bit # name value at reset description 15 mpwrd 1 main powerdown. if 1, powerdown. if 0, powerup. 14 spkfb 0* speaker #1 output filter bypass. if 1, the transmit lpf is bypassed in the speaker path; set the correspond- ing dma clock to 16 khz. if 0, the transmit lpf is enabled in the speaker path. note: the soc bits in the audio codec clock control register should also be modified. 13 hndfb 0* handset output filter bypass. if 1, the transmit lpf is bypassed in the handset path; set the correspond- ing dma clock to 16 khz. if 0, the transmit lpf is enabled in the handset path. note: the hoc bits in the audio codec clock control register should also be modified. 12 ainfb 0* analog input filter bypass. if 1, the receive bpf is bypassed in the audio input path; set the corre- sponding dma clock to 16 khz. if 0, the receive bpf is enabled in the audio input path. note: the ainc bits in the audio codec clock control register should also be modified. 11 spk2en 0 enables speaker #2 output channel. if 1, the speaker?s output driver is enabled. if 0, the output driver for the speaker output channel is disabled. 10 ole 0 output limit enable. when set, this bit causes the nominal full-scale output for the analog outputs to be limited to approximately half the normal value of 2.5 vp-p setting this bit has no effect on the receive gain. 9:7 rsvd reserved. * if the bpf is bypassed, output from the decimator must be shifted right by 2 bits (6 db attenuation) to avoid saturation going into the com- pander. similarly, if the lpf is bypassed in the speaker or handset path, input into the interpolator must be shifted left by 2 bits.
22 lucent technologies inc. phone-on-a-chip ip solution dsp T8301 internet protocol telephone advance data sheet december 2000 5 audio input/output circuitry (continued) table 11. aioc_reg analog audio i/o control ( continued) . bit # name value at reset description 6:4 pgas[2:0] 000 pga gain select. selects the gain for the programmable gain amplifier. see table 7 on page 17 for an explanation of the coding. 3 spken 0 enables the speaker output channel. if 1, the speaker?s output driver is enabled. if 0, the output driver for the speaker output channel is disabled. 2 aoutaen 0 enables the handset output channel. if 1, the handset output driver is enabled. if 0, the output driver for the handset output channel is disabled. 1:0 ainss 00 analog input source select. if 11, reserved. if 10, analog input source is from the microphone ( aincn, aincp ). if 01, analog input source is from the handset ( ainan ). if 00, mute (default after reset or powerup). table 12. audio codec clock control register (aclkc_reg) audio codec clock control register (aclkc_reg) address (0x4003) bit # 15:9 8:6 5:3 2:0 name rsvd soc(2:0) hoc(2:0) ainc(2:0) bit # name description 15:9 rsvd reserved. 8:6 soc(2:0) please refer to table 13 for bit field description. 5:3 hoc(2:0) please refer to table 13 for bit field description. 2:0 ainc(2:0) please refer to table 13 for bit field description. table 13. audio clock encoding audio clock encoding soc, hoc, ainc bit code description 000 0 hz. the clock for the channel is stopped. 001 8 khz clock is used for all audio codes except g.722. 010 16 khz clock is used for g.722 (must bypass filters). 011 reserved. 100 reserved. 101 reserved. 110 reserved. 111 supplies 1 mhz clock to dma. reserved for testing only.
lucent technologies inc. 23 advance data sheet december 2000 T8301 internet protocol telephone phone-on-a-chip ip solution dsp 6 dma input/output channels the discussions in this section pertain to circuitry that is outside of the dotted outline in figure 3 on page 8. there are three timed dma transfer blocks, each of which transfers data to/from the audio codec block from/to a 512 x 16-bit sram. these srams are two-port devices. one port is connected to the dsp1627 address and data bus, and the other is accessed by the dma controller. these memories transfer data to/from the audio codec block or aouta , ain , and sout . these dma blocks are capable of transferring a 16-bit word to/from the device?s a/d or d/a at the following rates, which are set up by programming the audio codec clock control register : 8 khz 16 khz each channel initiates a transfer between the audio codec block and its respective sram on the rising edge of the selected transfer clock. 6.1 dma operation the T8301 has three timed dma transfer channels. the dsp sets up a dma channel by writing a starting address and a transfer count into the setadr_reg (see table 15) and setcnt_reg (see table 16). the dsp then sets the channel?s go bit in the dmac_reg (see table 14). when the dma finishes its current transfer operation, indicated by the bsy bit in the dmac_reg going low, the dma will transfer the contents of the setadr_reg (see table 15) to the adrinc_reg (see table 17) and the cntdec_reg (see table 18) respectively. the go bit will be reset to zero and the bsy bit will be set to one, in the dmac_reg on completion of this transfer. when the rising edge of the transfer clock is detected, the dma controller will transfer a single word to/from memory and the audio codec block. the dma channel will then increment its address pointer adrinc_reg and decrement its counter cntdec_reg . at the completion of the number of transfers written into the transfer counter ( cntdec_reg = 0), the dma block will set its ion bit in the dmac_reg to 1 and reset its bsy bit to zero. if its ien bit is set, an interrupt to the dsp will occur. if the dsp has set the go bit which indicates that it has set up a new transfer or if the dsp responds (sets up a new transfer count and re-enables transfers) before the next rising edge of the transfer clock, data can be continuously transferred at the clocked rate. if the dsp is reading or writing to the memory that a timed dma is transferring to/from, the dma can be delayed by a clock cycle to allow the dsp to finish its access. 6.2 dma registers each dma channel has the following four registers: starting address register transfer count register working address increment register (read only) working count decrement register (read only) in addition, there is a control and status register that supports all three dma channels.
24 lucent technologies inc. phone-on-a-chip ip solution dsp T8301 internet protocol telephone advance data sheet december 2000 6 dma input/output channels (continued) table 14. dma control register dmac_reg dma control register (dmac_reg) address (0x4010) bit # 15 14 13 12 11 10 9 8 name rsvd ienspk ienhnd ienain rsvd ionspk ionhnd ionain bit # 7 654321 0 name rsvd spkbsy hndbsy ainbsy rsvd spkgo hndgo aingo bit # name description 15 rsvd reserved. 14 ienspk interrupt enable speaker output channel. 13 ienhnd interrupt enable handset output channel. 12 ienain interrupt enable analog input channel. 11 rsvd reserved. 10 ionspk interrupt on speaker dma channel. indicates a transfer has completed. a physical interrupt to the dsp will only occur if the ienspk bit is also set. the interrupt is cleared by a read operation. 9 ionhnd interrupt on handset dma channel. indicates a transfer has completed. a physical interrupt to the dsp will only occur if the ienhnd bit is also set. the interrupt is cleared by a read operation. 8 ionain interrupt on analog input dma channel. indicates a transfer has completed. a physi- cal interrupt to the dsp will only occur if the ienain bit is also set. the interrupt is cleared by a read operation. 7 rsvd reserved. 6 spkbsy speaker dma channel busy (read only). 5 hndbsy handset dma channel busy (read only). 4 ainbsy analog input dma channel busy (read only). 3 rsvd reserved. 2 spkgo dma start. starts the dma channel when set to 1, automatically reset to zero when a count of zero is reached by the dma transfer counter. 1 hndgo dma start. starts the dma channel when set to 1, automatically reset to zero when a count of zero is reached by the dma transfer counter. 0 aingo dma start. starts the dma channel when set to 1, automatically reset to zero when a count of zero is reached by the dma transfer counter. table 15. dma starting address register setadr_reg set dma address registers [ainsetadr_reg address (0x4014)] [hndsetadr_reg address (0x4018)] [spksetadr_reg address (0x401c)] bit # 15:9 8:0 name rsvd dma_address_set_up[8:0] table 16. dma transfer count register setcnt_reg set dma count registers [ainsetcnt_reg address (0x4015)] [hndsetcnt_reg address (0x4019)] [spksetcnt_reg address (0x401d)] bit # 15:9 8:0 name rsvd dma_count_set_up[8:0]
lucent technologies inc. 25 advance data sheet december 2000 phone-on-a-chip ip solution dsp T8301 internet protocol telephone 6 dma input/output channels (continued) table 17. dma address increment register adrinc_reg dma address increment registers (read only) [ainadrinc_reg address (0x4016)] [hndadrinc_reg address (0x401a)] [spkadrinc_reg address (0x401e)] bit # 15:9 8:0 name rsvd dma_address[8:0] table 18. dma transfer decrement register cntdec_reg dma count decrement registers (read only) [aincntdec_reg address (0x4017)] [hndcntdec_reg address (0x401b)] [spkcntdec_reg address (0x401f)] bit # 15:9 8:0 name rsvd dma_count[8:0]
26 lucent technologies inc. phone-on-a-chip ip solution dsp T8301 internet protocol telephone advance data sheet december 2000 7 hardware compander the discussions in this section pertain to circuitry that is outside of the dotted outline in figure 3 on page 8. the hardware compander performs companded-to-linear and linear-to-companded conversions. this alleviates the dsp from performing the functions in firmware. the compander supports both -law and a-law operations. a block diagram of the compander is shown in figure 6 on page 27. the compander consists of two write-only reg- isters: write_linear and write_companded . a configuration register ( config_compander ) and two read registers ( read _linear and read_ companded ) read the results. config_compand configures the compander for either -law or a-law conversion. upon reset, the register defaults to -law. the dsp performs a linear-to-companded conversion by writing the write_linear register and then reading the read-companded buffer. the companded value at the read buffer remains the same until a new linear value is written to the write_linear register . similarly, companded to linear is done by write_companded then read_linear. table 19. config_compander register compander configuration register (config_compander) bit 15:1 0 field reserved ? law after reset x1 = ? law 0 = a-law table 20. write_linear register write_linear bit 15:0 ? linear value table 21. write_companded register write_companded bit 15:0 ? companded value table 22. read_linear register read_linear bit 15:0 ? linear value table 23. read_companded register read_companded bit 15:0 ? companded value
lucent technologies inc. 27 advance data sheet december 2000 phone-on-a-chip ip solution dsp T8301 internet protocol telephone 7 hardware compander (continued) 5-8209(f) figure 6. hardware compander block diagram the config_compander register configures the compander for either -law or a-law conversion. upon reset, the register defaults to -law, see table 19 on page 26 . config_compander write_linear read_companded write_companded read_linear buffer buffer compander combinatorial logic - law dsp_d[15:0] dsp1627
28 lucent technologies inc. phone-on-a-chip ip solution dsp T8301 internet protocol telephone advance data sheet december 2000 8 electrical specifications 8.1 operating range specifications 8.2 analog and codec specifications * parameter supplied for reference purposes. * parameter supplied for reference purposes. table 24. operating range specifications parameter symbol min max unit ambient temperature range t a 070 c operating supply voltage v dd 4.75 5.25 v power consumption p ? 900 mw table 25. ainan specifications parameter conditions value source impedance* ac-coupled with a 0.2 f capacitor 1 k ? ?3 k ? input impedance with ac-coupled +2.5 vp-p input signal (max pga gain) 6 k ? ?12 k ? total harmonic distortion input signals 100 mv?2.5 vp-p 2% transmit idle channel noise pga set 12 db 20 dbrnc power supply rejection ratio ? 50 db table 26. aincp, aincn specifications parameter conditions value source impedance* ac-coupled w/ 0.2 f capacitor 1 k ? ? 3 k ? input impedance with ac-coupled 40 mvp-p 12 k ? ?20 k ? total gain ? 30 db 1 db total harmonic distortion input signals 1 mv?40 mv 2% total harmonic distortion input signals 1 mv?40 mv 2% table 27. aouta specifications parameter conditions value v out 0 dbm0 0.618 vrms (0.5 db) v out 3.14 dbm0 2.50 vp-p typical device impedance ? 150 ? total harmonic distortion (3.0 dbm0) ?35 db max ( a limit) ?40 db max total harmonic distortion (0.0 dbm0) 0.0 db max ( a limit) ?65 db max
lucent technologies inc. 29 advance data sheet december 2000 phone-on-a-chip ip solution dsp T8301 internet protocol telephone 8 electrical specifications (continued) note: maximum digital-to-analog converter range = 2.5 v. this translates into a peak-to-peak differential signal of 5.0 v. all signals measured differentially. . . 8.3 crystal specification see the dsp1627 digital signal processor data sheet for further information. table 28. speaker#1, speaker#2 specifications parameter conditions value v out 0 dbm0 1.236 vrms (0.5 db) v out 3.14 dbm0 5.00 vp-p typical device impedance ? 45 ? total gain ? 6 db 0.25 db total harmonic distortion ?35 db max ( a limit) ?40 db max total harmonic distortion 0.0 db max ( a limit) ?65 db max table 29. digital low-pass filters specifications parameter conditions value maximum ripple pass-band 300 hz signal frequency 3.0 khz 3% minimum attenuation 4 khz 30 db table 30. digital-to-analog converter specifications parameter conditions value range ? 16-bit monotonicity full operating range monotonic accuracy full operating range tbd full scale output ? 2.5 vp-p max voltage change 1-bit change ? 1.5 lsb input code ? two?s complement table 31. analog-to-digital converter specifications parameter conditions value range ? 16-bit monotonicity full operating range monotonic accuracy full operating range tbd max step-to-step size ? 1.5 lsb full scale input ? 2.5 vp-p output code ? two?s complement
30 lucent technologies inc. phone-on-a-chip ip solution dsp T8301 internet protocol telephone advance data sheet december 2000 9 jtag and hardware development system (hds) the jtag block contains logic for implementing the jtag/ ieee * p1149.1 standard. a four-signal test port provides a mechanism for accessing the dsp1627 core from remote test equipment or a remote hardware development system. the on-chip hds performs instruction breakpointing and branch tracing at full speed. using the jtag port, the breakpointing is set up and the trace history is read back. 9.1 tmode control for jcs/boundary-scan operation tmoden0, tmoden1, and tmoden2 are inputs used to determine test mode operation. of the eight possible combinations, modes 6 and 7 are significant during the development and production phases. 9.1.1 mode 7 operation (tmode = 7) this is the production mode. internal pull-up resistors (approximately 50 k ? ) will provide the logic level required. the three pins can be left floating (no external resistors are required). in this mode, boundary-scan is active. the ck8khz (pin 67), the ck2mhz (pin 98), and the cko (pin 99) are all dormant (high). 9.1.2 mode 6 operation (tmode = 6) the jcs tools (jtag communications system) are used in this mode. tmoden0 must be pulled low externally, tmoden1, and tmoden2 can both be left floating to enter this mode. the ck8khz (pin 67), the ck2mhz (pin 98), and the cko (pin 99) are active. should the user require access to any or all of the three clocks in production and still require boundary-scan capa- bilities for production test, a strong (external) pull-down resistor would be required on tmoden0 (1 k ? ). the pro- duction test must be able to pull tmoden0 high to allow access to the boundary-scan test. after the test is complete, the pin would normally be low (tmode 6) allowing the clocks to be active. 9.2 the principle of boundary-scan architecture each primary input signal and primary output signal is supplemented with a multipurpose memory element called a boundary-scan cell. cells on device primary inputs are referred to as input cells and cells on primary outputs are referred to as output cells. input and output is relative to the core logic of the device. at any time, only one register can be connected from tdi to tdo, e.g., the instruction register (ir), bypass, boundary-scan, ident, or even some appropriate register internal to the core logic; see figure 7. the selected register is identified by the decoded output of the instruction register. certain instructions are mandatory, such as extest (boundary-scan register selected), whereas others are optional, such as the idcode instruction (ident register selected). * ieee is a registered trademark of the institute of electrical and electronics engineers, inc.
lucent technologies inc. 31 advance data sheet december 2000 phone-on-a-chip ip solution dsp T8301 internet protocol telephone 9 jtag and hardware development system (hds) (continued) figure 7. boundary-scan architecture figure 7 shows the following elements: a set of four dedicated test pins, test data in (tdi), test mode select (tms), test clock (tck), test data out (tdo), and one optional test pin test reset (trstn). these pins are collectively referred to as the test access port (tap). a boundary-scan cell on each device?s primary input and primary output pin, connected internally to form a serial boundary-scan register (boundary-scan). a finite-state machine tap controller with inputs tck and tms. an n-bit (n = 4) instruction register (ir), holding the current instruction. a 1-bit bypass register (bypass). an optional 32-bit identification register (ident) capable of being loaded with a permanent device identification code. internal core logic identification register instruction register (ir) test mode select test clock tms tck test reset (trstn) test data out tdo tdi test data in bypass tap controller ieee 1149.1 chip architecture
32 lucent technologies inc. phone-on-a-chip ip solution dsp T8301 internet protocol telephone advance data sheet december 2000 9 jtag and hardware development system (hds) (continued) access to jtag (joint test action group) and boundary-scan will be initially provided through a single set of jtag pins. the pin definitions are as follows. debug mode, or boundary-scan mode is selected via the tmode pins as shown below. 9.2.1 boundary-scan instruction register the boundary-scan instruction register is 4 bits long and the capture value is 0001. the idcode values are as follows: version = 0000 (0x0) part = 0011011101000110 (0x 3746) manufacturer = 00000011101 (0x1d) table 32. boundary-scan pin functions pin boundary-scan debug comments 94 tdo (bscan) tdo (debug) ? 95 tck (bscan) tck (debug) pulled high internally 96 tms (bscan) tms (debug) pulled high internally 97 tdi (bscan) tdi (debug) ? 89 trstn (bscan) trstn (debug) pulled high internally table 33. debug mode pin name description comments 90 tmoden0 if 7 = boundary-scan if 6 = debug pulled high internally 91 tmoden1 pulled high internally 92 tmoden2 pulled high internally table 34. boundary-scan instruction register instruction binary code description extest 0000 places the boundary-scan register in extest mode. sample 0001 places the boundary-scan register in sample mode. idcode 0101 identification code. bypass 1111 places the bypass register in the scan chain.
lucent technologies inc. 33 advance data sheet december 2000 phone-on-a-chip ip solution dsp T8301 internet protocol telephone 9 jtag and hardware development system (hds) (continued) table 35. boundary-scan register description boundary-scan register bit pin pin name ball enabled state pin grouping control disable value 0 bio_e(0) ? controller ? ? ? 1 bio(0) 2 i/o bio_e(0) 0 high impedance 2 bio_e(1) ? controller ? ? ? 3 bio(1) 3 i/o bio_e(1) 0 high impedance 4 bio_e(2) ? controller ? ? ? 5 bio(2) 4 i/o bio_e(2) 0 high impedance 6 bio_e(3) ? controller ? ? ? 7 bio(3) 5 i/o bio_e(3) 0 high impedance 8 int0n 6 input ? ? ? 9 int1n 7 input ? ? ? 10 stopn 8 input ? ? ? 11 di1 9 input ? ? ? 12 do1_e ? controller ? ? ? 13 do1 12 i/o do1_e 0 high impedance 14 sync_e ? controller ? ? ? 15 sync 13 i/o sync_e 0 high impedance 16 iold_e ? controller ? ? ? 17 iold 14 i/o iold_e 0 high impedance 18 iock_e ? controller ? ? ? 19 iock 15 i/o iock_e 0 high impedance 20 dsp_a_e ? controller ? ? ? 21 a(15) 21 i/o a_e 0 high impedance 22 a(14) 22 i/o a_e 0 high impedance 23 a(13) 23 i/o a_e 0 high impedance 24 a(12) 24 i/o a_e 0 high impedance 25 a(11) 27 i/o a_e 0 high impedance 26 a(10) 28 i/o a_e 0 high impedance 27 a(9) 29 i/o a_e 0 high impedance 28 a(8) 30 i/o a_e 0 high impedance 29 a(7) 31 i/o a_e 0 high impedance 30 a(6) 32 i/o a_e 0 high impedance 31 a(5) 33 i/o a_e 0 high impedance 32 a(4) 34 i/o a_e 0 high impedance 33 a(3) 37 i/o a_e 0 high impedance 34 a(2) 38 i/o a_e 0 high impedance 35 a(1) 39 i/o a_e 0 high impedance 36 a(0) 40 i/o a_e 0 high impedance 37 i_csn 41 i/o a_e 0 high impedance 38 m_csn 42 i/o a_e 0 high impedance 39 x_csn 43 i/o a_e 0 high impedance 40 rwn 44 i/o a_e 0 high impedance
34 lucent technologies inc. phone-on-a-chip ip solution dsp T8301 internet protocol telephone advance data sheet december 2000 9 jtag and hardware development system (hds) (continued) boundary-scan register bit pin pin name ball enabled state pin grouping control disable value 41 d_e ? controller ? ? ? 42 d(15) 47 i/o d_e 0 high impedance 43 d(14) 48 i/o d_e 0 high impedance 44 d(13) 49 i/o d_e 0 high impedance 45 d(12) 50 i/o d_e 0 high impedance 46 d(11) 51 i/o d_e 0 high impedance 47 d(10) 52 i/o d_e 0 high impedance 48 d(9) 53 i/o d_e 0 high impedance 49 d(8) 54 i/o d_e 0 high impedance 50 d(7) 57 i/o d_e 0 high impedance 51 d(6) 58 i/o d_e 0 high impedance 52 d(5) 59 i/o d_e 0 high impedance 53 d(4) 60 i/o d_e 0 high impedance 54 d(3) 61 i/o d_e 0 high impedance 55 d(2) 62 i/o d_e 0 high impedance 56 d(1) 63 i/o d_e 0 high impedance 57 d(0) 64 i/o d_e 0 high impedance 58 clk_e ? controller ? ? ? 59 ck8khz 67 i/o clk_e 0 high impedance 60 stck_e ? controller ? ? ? 61 stck 68 i/o stck_e 0 high impedance 62 sti_e ? controller ? ? ? 63 sti1 70 i/o sti_e 0 high impedance 64 sto_e ? controller ? ? ? 65 sto1 69 i/o sto_e 0 high impedance 66 resetn_e ? controller ? ? ? 67 resetn 93 i/o resetn_e 0 high impedance 68 ck2mhz 98 i/o clk_e 0 high impedance 69 cko 99 i/o clk_e 0 high impedance table 35. boundary-scan register description (continued)
lucent technologies inc. 35 advance data sheet december 2000 T8301 internet protocol telephone phone-on-a-chip ip solution dsp notes
lucent technologies inc. reserves the right to make changes to the product(s) or information contained herein without notice. n o liability is assumed as a result of their use or application. no rights under any patent accompany the sale of any such product(s) or information. phone-on-a-chip is a trademark of lucent technologies inc. copyright ? 2000 lucent technologies inc. all rights reserved printed in u.s.a. december 2000 ds01-025ipt (replaces ds00-030ipt-3) for additional information, contact your microelectronics group account manager or the following: internet: http://www.lucent.com/micro e-mail: docmaster@micro.lucent.com n. america: microelectronics group, lucent technologies inc., 555 union boulevard, room 30l-15p-ba, allentown, pa 18109-3286 1-800-372-2447 , fax 610-712-4106 (in canada: 1-800-553-2448 , fax 610-712-4106) asia pacific: microelectronics group, lucent technologies singapore pte. ltd., 77 science park drive, #03-18 cintech iii, singap ore 118256 tel. (65) 778 8833 , fax (65) 777 7495 china: microelectronics group, lucent technologies (china) co., ltd., a-f2, 23/f, zao fong universe building, 1800 zhong shan xi road, shanghai 200233 p. r. china tel. (86) 21 6440 0468, ext. 325 , fax (86) 21 6440 0652 japan: microelectronics group, lucent technologies japan ltd., 7-18, higashi-gotanda 2-chome, shinagawa-ku, tokyo 141, japan tel. (81) 3 5421 1600 , fax (81) 3 5421 1700 europe: data requests: microelectronics group dataline: tel. (44) 7000 582 368 , fax (44) 1189 328 148 technical inquiries: germany: (49) 89 95086 0 (munich), united kingdom: (44) 1344 865 900 (ascot), france: (33) 1 40 83 68 00 (paris), sweden: (46) 8 594 607 00 (stockholm), finland: (358) 9 3507670 (helsinki), italy: (39) 02 6608131 (milan), spain: (34) 1 807 1441 (madrid)
data sheet march 2000 dsp1627 digital signal processor 1 features n optimized for digital cellular applications with a bit manip- ulation unit for higher coding efficiency. n on-chip, programmable, pll clock synthesizer. n 14 ns and 11 ns instruction cycle times at 5 v, 10 ns in- struction cycle time at 3.0 v, and 20 ns and 12.5 ns in- struction cycle times at 2.7 v, respectively. n mask-programmable memory map option: the dsp1627x36 features 36 kwords on-chip rom. the dsp1627x32 features 32 kwords on-chip rom and ac- cess to 16 kwords external rom in the same map. both feature 6 kwords on-chip, dual-port ram and a secure option for on-chip rom. n low power consumption: <5.5 mw/mips typical at 5 v. <1.5 mw/mips typical at 2.7 v. n flexible power management modes: standard sleep: 0.5 mw/mips at 5 v. 0.12 mw/mips at 2.7 v. sleep with slow internal clock: 1.4 mw at 5 v. 0.4 mw at 2.7 v. hardware stop (pin halts dsp): <20 m a. n mask-programmable clock options: crystal oscillator, small signal, and cmos. n low-profile tqfp package (1.5 mm) available. n sequenced accesses to x and y external memory. n object code compatible with the dsp1617. n single-cycle squaring. n 16 x 16-bit multiplication and 36-bit accumulation in one instruction cycle. n instruction cache for high-speed, program-efficient, zero- overhead looping. n dual 25 mbits/s serial i/o ports with multiprocessor capa- bility16-bit data channel, 8-bit protocol channel. n 8-bit parallel host interface: supports 8- or 16-bit transfers. motorola * or intel ? compatible. n 8-bit control i/o interface. n 256 memory-mapped i/o ports. n ieee ? p1149.1 test port (jtag boundary scan). n full-speed in-circuit emulation hardware development system on-chip. n supported by dsp1627 software and hardware develop- ment tools. 2 description the dsp1627 is lucent technologies microelectronics group first digital signal processor offering 100 mips oper- ation at 3.0 v and 80 mips operation at 2.7 v with a reduc- tion in power consumption. designed specifically for applications requiring low power dissipation in digital cellu- lar systems, the dsp1627 is a signal-coding device that can be programmed to perform a wide variety of fixed-point sig- nal processing functions. the device is based on the dsp1600 core with a bit manipulation unit for enhanced sig- nal coding efficiency. the dsp1627 includes a mix of pe- ripherals specifically intended to support processing- intensive but cost-sensitive applications in the area of digital wireless communications. the dsp1627x36 contains 36 kwords of internal rom (irom), but it doesnt support the use of irom and external rom (erom) in the same memory map. the dsp1627x32 supports the use of 32 kwords of irom with 16 kwords of erom in the same map. both devices contain 6 kwords of dual-port ram (dpram), which allows simultaneous ac- cess to two ram locations in a single instruction cycle. the dsp1627 is object code compatible with the dsp1617, while providing more memory and architectural enhance- ments including an on-chip clock synthesizer and an 8-bit parallel host interface for hardware flexibility. the dsp1627 supports 2.7 v, 3.0 v, and 5 v operation and flexible power management modes required for portable cellular terminals. several control mechanisms achieve low- power operation, including a stop pin for placing the dsp into a fully static, halted state and a programmable power control register used to power down unused on-chip i/o units. these power management modes allow for trade-offs between power reduction and wake-up latency require- ments. during system standby, power consumption is re- duced to less than 20 m a. the on-chip clock synthesizer can be driven by an external clock whose frequency is a fraction of the instruction rate. the device is packaged in a 100-pin bqfp or a 100-pin tqfp and is available with 14 ns and 11 ns instruction cycle times at 5 v, 10 ns instruction cycle times at 3.0 v, and 20 ns and 12.5 ns instruction cycle times at 2.7 v, respec- tively. * motorola is a registered trademark of motorola, inc. ? intel is a registered trademark of intel corp. ? ieee is a registered trademark of the institute of electrical and electronics engineers, inc.
data sheet dsp1627 digital signal processor march 2000 2 lucent technologies inc. table of contents contents page contents page 1 features.............................................................. 1 2 description .......................................................... 1 3 pin information.................................................... 3 4 hardware architecture ........................................ 7 4.1 dsp1627 architectural overview ............. 7 4.2 dsp1600 core architectural overview .. 10 4.3 interrupts and trap ................................. 11 4.4 memory maps and wait-states .............. 16 4.5 external memory interface (emi)............ 18 4.6 bit manipulation unit (bmu) ................... 19 4.7 serial i/o units (sios) ............................ 19 4.8 parallel host interface (phif)................. 22 4.9 bit input/output unit (bio)...................... 23 4.10 timer ...................................................... 23 4.11 jtag test port....................................... 24 4.12 clock synthesis ...................................... 26 4.13 power management ............................... 29 5 software architecture ....................................... 36 5.1 instruction set......................................... 36 5.2 register settings .................................... 45 5.3 instruction set formats .......................... 55 6 signal descriptions ........................................... 61 6.1 system interface..................................... 61 6.2 external memory interface ..................... 63 6.3 serial interface #1 .................................. 64 6.4 parallel host interface or serial interface #2 and control i/o interface .... 65 6.5 control i/o interface ............................... 65 6.6 jtag test interface ............................... 66 7 mask-programmable options ........................... 67 7.1 input clock options ................................ 67 7.2 memory map options ............................. 67 7.3 rom security options............................ 67 8 device characteristics ...................................... 68 8.1 absolute maximum ratings.................... 68 8.2 handling precautions ............................. 68 8.3 recommended operating conditions .... 68 8.4 package thermal considerations .......... 69 9 electrical characteristics and requirements .... 70 9.1 power dissipation................................... 73 10 timing characteristics for 5 v operation .......... 75 10.1 dsp clock generation ........................... 76 10.2 reset circuit ........................................... 77 10.3 reset synchronization............................ 78 10.4 jtag i/o specifications.......................... 79 10.5 interrupt .................................................. 80 10.6 bit input/output (bio) ............................. 81 10.7 external memory interface...................... 82 10.8 phif specifications ................................ 86 10.9 serial i/o specifications.......................... 92 10.10 multiprocessor communication .............. 97 11 timing characteristics for 3.0 v operation ....... 98 11.1 dsp clock generation............................ 99 11.2 reset circuit ......................................... 100 11.3 reset synchronization.......................... 101 11.4 jtag i/o specifications........................ 102 11.5 interrupt ................................................ 103 11.6 bit input/output (bio) ........................... 104 11.7 external memory interface.................... 105 11.8 phif specifications .............................. 109 11.9 serial i/o specifications........................ 115 11.10 multiprocessor communication ............ 120 12 timing characteristics for 2.7 v operation ..... 121 12.1 dsp clock generation.......................... 122 12.2 reset circuit ......................................... 123 12.3 reset synchronization.......................... 124 12.4 jtag i/o specifications........................ 125 12.5 interrupt ................................................ 126 12.6 bit input/output (bio) ........................... 127 12.7 external memory interface.................... 128 12.8 phif specifications .............................. 132 12.9 serial i/o specifications........................ 138 12.10 multiprocessor communication ............ 143 13 crystal electrical characteristics and requirements.................................................. 144 13.1 external components for the crystal oscillator............................................... 144 13.2 power dissipation ................................. 144 13.3 lc network design for third overtone crystal circuits...................... 147 13.4 frequency accuracy considerations .... 149 14 outline diagrams ............................................ 152 14.1 100-pin bqfp (bumpered quad flat pack).............................................. 152 14.2 100-pin tqfp (thin quad flat pack)... 153
data sheet march 2000 dsp1627 digital signal processor lucent technologies inc. 3 3 pin information figure 1. dsp1627 bqfp pin diagram dsp1627 20 10 30 90 80 70 v ss sync1 do1 old1 ock1 ick1 ild1 v ss di1 v dd ibf1 obe1 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 v dd v ss db4 db2 db1 db0 v ss io db3 v ss v dd ab11 ab10 ab9 ab8 ab7 v ss eramhi erom rwn exm ab14 ab12 eramlo v dd sadd1 doen1 ock2/pcsn do2/pstat sync2/pbsel ild2/pids old2/pods ibf2/pibf obe2/pobe di2/pb1 v ss doen2/pb2 sadd2/pb3 v dd iobit0/pb4 iobit1/pb5 iobit2/pb6 iobit3/pb7 vec3/iobit4 vec2/iobit5 vec1/iobit6 vec0/iobit7 v ss ick2/pb0 v ssa cki2 cki v dda tdo tms v dd cko trap stop iack v ss int0 int1 ab0 ab1 ab2 ab3 ab4 ab5 ab6 rstb tck 100 v dd 60 50 40 pin #1 identifier zone tdi ab13 v dd ab15 5-4218 (f).b
data sheet dsp1627 digital signal processor march 2000 4 lucent technologies inc. 3 pin information (continued) figure 2. dsp1627 tqfp pin diagram v dd db5 db6 db7 db8 db9 db10 v ss db11 db12 db13 db14 db15 v dd obe1 ibf1 v ss di1 ild1 ick1 ock1 old1 do1 sync1 v ss 100 90 80 v dd ab6 ab5 ab4 ab3 ab2 ab0 int1 int0 v ss iack stop trap rstb cko v dd tck tms tdo tdi v dda cki cki2 v ssa ab1 30 40 50 60 70 v dd sadd1 doen1 ock2/pcsn do2/pstat sync2/pbsel ild2/pids old2/pods ibf2/pibf obe2/pobe ick2/pb0 v ss doen2/pb2 sadd2/pb3 v dd iobit0/pb4 iobit1/pb5 iobit2/pb6 iobit3/pb7 vec3/iobit4 vec2/iobit5 vec1/iobit6 vec0/iobit7 v ss di2/pb1 v ss db4 db3 db2 db1 db0 io eramhi v dd eramlo erom rwn v ss exm ab15 ab14 v dd ab13 ab12 ab11 ab10 ab9 ab8 ab7 v ss 1 10 20 dsp1627 5-4219 (f).b
data sheet march 2000 dsp1627 digital signal processor lucent technologies inc. 5 3 pin information (continued) functional descriptions of pins 1100 are found in section 6, signal descriptions. the functionality of pins 61 and 62 (tqfp pins 48 and 49) are mask-programmable (see section 7, mask-programmable options). input levels on all i and i/o type pins are designed to remain at full cmos levels when not driven by the dsp. * 3-states when rstb = 0, or by jtag control. ? 3-states when rstb = 0 and int0 = 1. output = 1 when rstb = 0 and int0 = 0, except cko which is free-running. ? pull-up devices on input. 3-states by jtag control. ** see section 7, mask-programmable options. ?? for sio multiprocessor applications, add 5 k w external pull-up resistors to sadd1 and/or sadd2 for proper initialization. table 1. pin descriptions bqfp pin tqfp pin symbol type name/function 1, 2, 3, 4, 5, 7, 8, 9, 10, 11, 12, 15, 16, 17, 18, 19 88, 89, 90, 91, 92, 94, 95, 96, 97, 98, 99, 2, 3, 4, 5, 6 db[15:0] i/o* external memory data bus db[15:0]. 20 7 io o ? data address 0x4000 to 0x40ff i/o enable. 21 8 eramhi o ? data address 0x8000 to 0xffff external ram enable. 23 10 eramlo o ? data address 0x4100 to 0x7fff external ram enable. 24 11 erom o ? program address external rom enable. 25 12 rwn o ? read/write not. 27 14 exm i external rom enable. 28, 29, 31, 32, 33, 34, 35, 36, 37, 40, 41, 42, 43, 44, 45, 46 15, 16, 18, 19, 20, 21, 22, 23, 24, 27, 28, 29, 30, 31, 32, 33 ab[15:0] o* external memory address bus 150. 47 34 int1 i vectored interrupt 1. 48 35 int0 i vectored interrupt 0. 50 37 iack o* interrupt acknowledge. 51 38 stop i stop input clock. 52 39 trap i/o* nonmaskable program trap/breakpoint indication. 53 40 rstb i reset bar. 54 41 cko o ? processor clock output. 56 43 tck i jtag text clock. 57 44 tms i ? jtag test mode select. 58 45 tdo o jtag test data output. 59 46 tdi i ? jtag test data input. mask-programmable input clock option cmos small signal crystal oscillator cmos 61 48 cki** i cki v ac xlo, 10 pf capacitor to v ss cki 62 49 cki2** i v ssa v cm xhi, 10 pf capacitor to v ss open 65 52 vec0/iobit7 i/o* vectored interrupt indication 0/status/control bit 7. 66 53 vec1/iobit6 i/o* vectored interrupt indication 1/status/control bit 6. 67 54 vec2/iobit5 i/o* vectored interrupt indication 2/status/control bit 5. 68 55 vec3/iobit4 i/o* vectored interrupt indication 3/status/control bit 4.
data sheet dsp1627 digital signal processor march 2000 6 lucent technologies inc. 3 pin information (continued) functional descriptions of pins 1100 are found in section 6, signal descriptions. * 3-states when rstb = 0, or by jtag control. ? 3-states when rstb = 0 and int0 = 1. output = 1 when rstb = 0 and int0 = 0. pull-up devices on input. ? 3-states by jtag control. ** see section 7, mask-programmable options. ?? for sio multiprocessor applications, add 5 k w external pull-up resistors to sadd1 and/or sadd2 for proper initialization. table 1. pin descriptions (continued) bqfp pin tqfp pin symbol type name/function 69 56 iobit3/pb7 i/o* status/control bit 3/phif data bus bit 7. 70 57 iobit2/pb6 i/o* status/control bit 2/phif data bus bit 6. 71 58 iobit1/pb5 i/o* status/control bit 1/phif data bus bit 5. 72 59 iobit0/pb4 i/o* status/control bit 0/phif data bus bit 4. 74 61 sadd2/pb3 ?? i/o* sio2 multiprocessor address/phif data bus bit 3. 75 62 doen2/pb2 i/o* sio2 data output enable/phif data bus bit 2. 77 64 di2/pb1 i/o* sio2 data input/phif data bus bit 1. 78 65 ick2/pb0 i/o* sio2 input clock/phif data bus bit 0. 79 66 obe2/pobe o* sio2 output buffer empty/phif output buffer empty. 80 67 ibf2/pibf o* sio2 input buffer full/phif input buffer full. 81 68 old2/pods i/o* sio2 output load/phif output data strobe. 82 69 ild2/pids i/o* sio2 input load/phif input data strobe. 83 70 sync2/pbsel i/o* sio2 multiprocessor synchronization/phif byte select. 84 71 do2/pstat i/o* sio2 data output/phif status register select. 85 72 ock2/pcsn i/o* sio2 output clock/phif chip select not. 86 73 doen1 i/o* sio1 data output enable. 87 74 sadd1 ?? i/o* sio1 multiprocessor address. 90 77 sync1 i/o* sio1 multiprocessor synchronization. 91 78 do1 o* sio1 data output. 92 79 old1 i/o* sio1 output load. 93 80 ock1 i/o* sio1 output clock. 94 81 ick1 i/o* sio1 input clock. 95 82 ild1 i/o* sio1 input load. 96 83 di1 i sio1 data input. 98 85 ibf1 o* sio1 input buffer full. 99 86 obe1 o* sio1 output buffer empty. 6, 15, 26, 38, 49, 64, 76, 89, 97 93, 1, 13, 25, 36, 51, 63, 76, 84 v ss p ground. 14, 22, 30, 39, 55, 73, 88, 100 100, 9, 17, 26, 42, 60, 75, 87 v dd p power supply. 60 47 v dda p analog power supply. 63 50 v ssa p analog ground.
data sheet march 2000 dsp1627 digital signal processor lucent technologies inc. 7 4 hardware architecture the dsp1627 device is a 16-bit, fixed-point program- mable digital signal processor (dsp). the dsp1627 consists of a dsp1600 core to g ether with on-chip mem- ory and peripherals. added architectural features give the dsp1627 high program efficiency for signal coding applications. 4.1 dsp1627 architectural overview figure 3 shows a block diagram of the dsp1627. the fol- lowing modules make up the dsp1627. dsp1600 core the dsp1600 core is the heart of the dsp1627 chip. the core contains data and address arithmetic units, and control for on-chip memory and peripherals. the core provides support for external memory wait-states and on- chip, dual-port ram and features vectored interrupts and a trap mechanism. dual-port ram (dpram) this module contains six banks of zero wait-state mem- ory. each bank consists of 1k 16-bit words and has sep- arate address and data ports to the instruction/coefficient and data memory spaces. a program can reference memory from either space. the dsp1600 core automat- ically performs the required multiplexing. if references to both ports of a single bank are made simultaneously, the dsp1600 core automatically inserts a wait-state and per- forms the data port access first, followed by the instruc- tion/coefficient port access. a program can be downloaded from slow, off-chip mem- ory into dpram, and then executed without wait-states. dpram is also useful for improving convolution perfor- mance in cases where the coefficients are adaptive. since dpram can be downloaded through the jtag port, full-speed remote in-circuit emulation is possible. dpram can also be used for downloading self-test code via the jtag port. read-only memory (rom) the dsp1627x36 contains 36k 16-bit words of zero wait-state mask-programmable rom for program and fixed coefficients. similarly, the dsp1627x32 has 32k 16-bit words of rom and access to 16 kwords of exter- nal rom. external memory multiplexer (emux) the emux is used to connect the dsp1627 to external memory and i/o devices. it supports read/write opera- tions from/to instruction/coefficient memory (x memory space) and data memory (y memory space). the dsp1600 core automatically controls the emux. instruc- tions can transparently reference external memory from either set of internal buses. a sequencer allows a single instruction to access both the x and the y external mem- ory spaces. clock synthesis the dsp powers up with a 1x input clock (cki/cki2) as the source for the processor clock. an on-chip clock syn- thesizer (pll) can also be used to generate the system clock for the dsp, which will run at a frequency multiple of the input clock. the clock synthesizer is deselected and powered down on reset. for low-power operation, an internally generated slow clock can be used to drive the dsp. if both the clock synthesizer and the internally gen- erated slow clock are selected, the slow clock will drive the dsp; however, the synthesizer will continue to run. the clock synthesizer and other programmable clock sources are discussed in section 4.12. the use of these programmable clock sources for power management is discussed in section 4.13. bit manipulation unit (bmu) the bmu extends the dsp1600 core instruction set to provide more efficient bit operations on accumulators. the bmu contains logic for barrel shifting, normalization, and bit field insertion/extraction. the unit also contains a set of 36-bit alternate accumulators. the data in the al- ternate accumulators can be shuffled with the data in the main accumulators. flags returned by the bmu mesh seamlessly with the dsp1600 conditional instructions. bit input/output (bio) the bio provides convenient and efficient monitoring and control of eight individually configurable pins. when configured as outputs, the pins can be individually set, cleared, or toggled. when configured as inputs, individu- al pins or combinations of pins can be tested for patterns. flags returned by the bio mesh seamlessly with condi- tional instructions. serial input/output units (sio and sio2) sio and sio2 offer asynchronous, full-duplex, double- buffered channels that operate at up to 25 mbits/s (for 20 ns instruction cycle in a nonmultiprocessor configura- tion), and easily interface with other lucent technologies fixed-point dsps in a multiple-processor environment. commercially available codecs and time-division multi- plex (tdm) channels can be interfaced to the serial i/o ports with few, if any, additional components. sio2 is identical to sio. an 8-bit serial protocol channel may be transmitted in ad- dition to the address of the called processor in multipro- cessor mode. this feature is useful for transmitting high- level framing information or for error detection and cor- rection. sio2 and bio are pin-multiplexed with the phif.
data sheet dsp1627 digital signal processor march 2000 8 lucent technologies inc. 4 hardware architecture (continued) * these registers are accessible through the pins only. ? 36k x 16 for the dsp1627x36; 32k x 16 for the dsp1627x32. figure 3. dsp1627 block diagram tdo tck tms m u x dsp1600 core rwn exm erom eramhi ab[15:0] db[15:0] i/o vec[3:0] or iobit[7:4] do2 or pstat old2 or pods ock2 or pcsn obe2 or pobe sync2 or pbsel ick2 or pb0 ild2 or pids di2 or pb1 ibf2 or pibf doen2 or pb2 sadd2 or pb3 io bit[3:0] or pb[7:4] cki cki2 cko rstb stop trap int[1:0] iack di1 ick1 ild1 ibf1 do1 ock1 old1 obe1 sync1 sadd1 doen1 external memory interface & emux ioc dual-port ram 6k x 16 rom 36k/32k x 16 ? eramlo yab ydb xdb xab bmu aa0 aa1 ar0 ar1 ar2 ar3 idb phif phifc pstat * pdx0(in) pdx0(out) bio sbit cbit sio2 sdx2(out) srta2 tdms2 sdx2(in) sioc2 saddx2 sio sdx(out) srta tdms sdx(in) sioc saddx timer timerc timer0 hds breakpoint * jtag boundary scan * jtag jcon * id * bypass * trace * powerc tdi pllc trst 5-4142 (f).f
data sheet march 2000 dsp1627 digital signal processor lucent technologies inc. 9 4 hardware architecture (continued) table 2. dsp1627 block diagram legend symbol name aa<01> alternate accumulators. ar<03> auxiliary bmu registers. bio bit input/output unit. bmu bit manipulation unit. breakpoint four instruction breakpoint registers. bypass jtag bypass register. cbit control register for bio. emux external memory multiplexer. hds hardware development system. id jtag device identification register. idb internal data bus. ioc i/o configuration register. jcon jtag configuration registers. jtag 16-bit serial/parallel register. pdx0(in) parallel data transmit input register 0. pdx0(out) parallel data transmit output register 0. phif parallel host interface. phifc parallel host interface control register. pllc phase-locked loop control register. powerc power control register. pstat parallel host interface status register. rom internal rom (36 kwords for dsp1627x36, 32 kwords for dsp1627x32). saddx multiprocessor protocol register. saddx2 multiprocessor protocol register for sio2. sbit status register for bio. sdx(in) serial data transmit input register. sdx2(in) serial data transmit input register for sio2. sdx(out) serial data transmit output register. sdx2(out) serial data transmit output register for sio2. sio serial input/output unit. sio2 serial input/output unit #2. sioc serial i/o control register. sioc2 serial i/o control register for sio2. srta serial receive/transmit address register. srta2 serial receive/transmit address register for sio2. tdms serial i/o time-division multiplex signal control register. tdms2 serial i/o time-division multiplex signal control register for sio2. timer programmable timer. timer0 timer running count register. timerc timer control register. trace program discontinuity trace buffer. xab program memory address bus. xdb program memory data bus. yab data memory address bus. ydb data memory data bus.
data sheet dsp1627 digital signal processor march 2000 10 lucent technologies inc. 4 hardware architecture (continued) parallel host interface (phif) the phif is a passive, 8-bit parallel port which can in- terface to an 8-bit bus containing other lucent technol- ogies dsps (e.g., dsp1620, dsp1627, dsp1628, dsp1629, dsp1611, dsp1616, dsp1617, dsp1618), microprocessors, or peripheral i/o devices. the phif port supports either motorola or intel protocols, as well as 8-bit or 16-bit transfers, configured in software. the port data rate depends upon the instruction cycle rate. a 25 ns instruction cycle allows the phif to support data rates up to 11.85 mbytes/s, assuming the external host device can transfer 1 byte of data in 25 ns. the phif is accessed in two basic modes: 8-bit or 16-bit mode. in 16-bit mode, the host determines an ac- cess of the high or low byte. in 8-bit mode, only the low byte is accessed. software-programmable features al- low for a glueless host interface to microprocessors (see section 4.8, parallel host interface). timer the timer can be used to provide an interrupt at the ex- piration of a programmed interval. the interrupt may be single or repetitive. more than nine orders of magnitude of interval selection are provided. the timer may be stopped and restarted at any time. hardware development system (hds) module the on-chip hds performs instruction breakpointing and branch tracing at full speed without additional off- chip hardware. using the jtag port, the breakpointing is set up, and the trace history is read back. the port works in conjunction with the hds code in the on-chip rom and the hardware and software in a remote com- puter. the hds code must be linked to the user's appli- cation code and reside in the first 4 kwords of rom. the on-chip hds cannot be used with the secure rom masking option (see section 7.3, rom security op- tions). four hardware breakpoints can be set on instruction ad- dresses. a counter can be preset with the number of breakpoints to receive before trapping the core. break- points can be set in interrupt service routines. alternate- ly, the counter can be preset with the number of cache instructions to execute before trapping the core. every time the program branches instead of executing the next sequential instruction, the addresses of the in- structions executed before and after the branch are caught in circular memory. the memory contains the last four pairs of program discontinuities for hardware tracing. in systems with multiple processors, the processors may be configured such that any processor reaching a breakpoint will cause all the other processors to be trapped (see section 4.3, interrupts and trap). pin multiplexing in order to allow flexible device interfacing while main- taining a low package pin count, the dsp1627 multi- plexes 16 package pins between bio, phif, vec[3:0], and sio2. upon reset, the vectored interrupt indication signals, vec[3:0], are connected to the package pins while iobit[4:7] are disconnected. setting bit 12, ebioh, of the ioc register connects iobit[4:7] to the package pins and disconnects vec[3:0]. upon reset, the parallel host interface (phif) is con- nected to the package pins while the second serial port (sio2) and iobit[3:0] are disconnected. setting bit 10, esio2, of the ioc register connects the sio2 and iobit[3:0] and disconnects the phif. power management many applications, such as portable cellular terminals, require programmable sleep modes for power manage- ment. there are three different control mechanisms for achieving low-power operation: the powerc control reg- ister, the stop pin, and the await bit in the alf register. the await bit in the alf register allows the processor to go into a power-saving standby mode until an interrupt occurs. the powerc register configures various power- saving modes by controlling internal clocks and periph- eral i/o units. the stop pin controls the internal pro- cessor clock. the various power management options may be chosen based on power consumption and/or wake-up latency requirements. 4.2 dsp1600 core architectural overview figure 4 shows a block diagram of the dsp1600 core. system cache and control section (sys) this section of the core contains a 15-word cache mem- ory and controls the instruction sequencing. it handles vectored interrupts and traps, and also provides decod- ing for registers outside of the dsp1600 core. sys stretches the processor cycle if wait-states are required (wait-states are programmable for external memory ac- cesses). sys sequences downloading via jtag of self- test programs to on-chip, dual-port ram. the cache loop iteration count can be specified at run time under program control as well as at assembly time.
data sheet march 2000 dsp1627 digital signal processor lucent technologies inc. 11 4 hardware architecture (continued) data arithmetic unit (dau) the data arithmetic unit (dau) contains a 16 x 16-bit parallel multiplier that generates a full 32-bit product in one instruction cycle. the product can be accumulated with one of two 36-bit accumulators. the accumulator data can be directly loaded from, or stored to, memory in two 16-bit words with optional saturation on overflow. the arithmetic logic unit (alu) supports a full set of arithmetic and logical operations on either 16- or 32-bit data. a standard set of flags can be tested for condition- al alu operations, branches, and subroutine calls. this procedure allows the processor to perform as a power- ful 16- or 32-bit microprocessor for logical and control applications. the available instruction set is fully com- patible with the dsp1617 instruction set. see section 5.1 for more information on the instruction set. the user also has access to two additional dau regis- ters. the psw register contains status information from the dau (see table 26, processor status word regis- ter). the arithmetic control register, auc, is used to con- figure some of the features of the dau (see table 27) including single-cycle squaring. the auc register align- ment field supports an arithmetic shift left by one and left or right by two. the auc register is cleared by reset. the counters c0 to c2 are signed, 8 bits wide, and may be used to count events such as the number of times the program has executed a sequence of code. they are controlled by the conditional instructions and pro- vide a convenient method of program looping. y space address arithmetic unit (yaau) the yaau supports high-speed, register-indirect, com- pound, and direct addressing of data (y) memory. four general-purpose, 16-bit registers, r0 to r3, are available in the yaau. these registers can be used to supply the read or write addresses for y space data. the yaau also decodes the 16-bit data memory address and out- puts individual memory enables for the data access. the yaau can address the six 1 kword banks of on- chip dpram or three external data memory segments. up to 48 kwords of off-chip ram are addressable, with 16k addresses reserved for internal ram. two 16-bit registers, rb and re, allow zero-overhead modulo addressing of data for efficient filter implemen- tations. two 16-bit signed registers, j and k, are used to hold user-defined postmodification increments. fixed increments of +1, C1, and +2 are also available. four compound-addressing modes are provided to make read/write operations more efficient. the yaau allows direct (or indexed) addressing of data memory. in direct addressing, the 16-bit base register (ybase) supplies the 11 most significant bits of the ad- dress. the direct data instruction supplies the remaining 5 bits to form an address to y memory space and also specifies one of 16 registers for the source or destina- tion. x space address arithmetic unit (xaau) the xaau supports high-speed, register-indirect, in- struction/coefficient memory addressing with postmodi- fication of the register. the 16-bit pt register is used for addressing coefficients. the signed register i holds a user-defined postincrement. a fixed postincrement of +1 is also available. register pc is the program counter. registers pr and pi hold the return address for subroutine calls and interrupts, respectively. the xaau decodes the 16-bit instruction/coefficient ad- dress and produces enable signals for the appropriate x memory segment. the addressable x segments are internal rom (up to 36 kwords for the dsp1627x36, up to 32 kwords for the dsp1627x32), six 1k banks of dpram, and external rom. the locations of these memory segments depend upon the memory map selected (see table 5). a security mode can be selected by mask option. this prevents unauthorized access to the contents of on-chip rom (see section 7, mask-programmable options). 4.3 interrupts and trap the dsp1627 supports prioritized, vectored interrupts and a trap. the device has eight internal hardware sources of program interrupt and two external interrupt pins. additionally, there is a trap pin and a trap signal from the hardware development system (hds). a soft- ware interrupt is available through the icall instruction. the icall instruction is reserved for use by the hds. each of these sources of interrupt and trap has a unique vector address and priority assigned to it. dsp16a in- terrupt compatibility is not maintained. the software interrupt and the traps are always enabled and do not have a corresponding bit in the ins register. other vectored interrupts are enabled in the inc register (see table 29, interrupt control (inc) register) and monitored in the ins register (see table 30, interrupt status (ins) register). when the dsp1627 goes into an interrupt or trap service routine, the iack pin is assert- ed. in addition, pins vec[3:0] encode which interrupt/ trap is being serviced. table 4 details the encoding used for vec[3:0].
data sheet dsp1627 digital signal processor march 2000 12 lucent technologies inc. 4 hardware architecture (continued) figure 4. dsp1600 core block diagram 5-1741 (f).b psw (16) auc (16) control cache cloop (7) inc (16) ins (16) alf (16) mwait (16) sys xdb xab idb yab ydb r0 (16) r1 (16) r2 (16) r3 (16) j (16) k (16) re (16) yaau rb (16) adder mux cmp ybase (16) pc (16) pt (16) pi (16) i (16) adder xaau extract/sat x (16) yh (16) yl (16) 16 x 16 mpy p (32) shift (C2, 0, 1, 2) c0 (8) c2 (8) c1 (8) 16 alu/shift a0 (36) a1 (36) 36 32 mux dau mux C1, 0, 1, 2 bridge mux 1 pr (16)
data sheet march 2000 dsp1627 digital signal processor lucent technologies inc. 13 4 hardware architecture (continued) table 3. dsp1600 core block diagram legend symbol name 16 x 16 mpy 16-bit x 16-bit multiplier. a0a1 accumulators 0 and 1 (16-bit halves specified as a0, a0l, a1, and a1l) * . * f3 alu instructions with immediates require specifying the high half of the accumulators as a0h and a1h. alf await, lowpr, flags. alu/shift arithmetic logic unit/shifter. auc arithmetic unit control. c0c2 counters 02. cloop cache loop count. cmp comparator. dau digital arithmetic unit. i increment register for the x address space. idb internal data bus. inc interrupt control. ins interrupt status. j increment register for the y address space. k increment register for the y address space. mux multiplexer. mwait external memory wait-states register. p product register (16-bit halves specified as p, pl). pc program counter. pi program interrupt return register. pr program return register. psw processor status word. pt x address space pointer. r0r3 y address space pointers. rb modulo addressing register (begin address). re modulo addressing register (end address). sys system cache and control section. x multiplier input register. xaau x space address arithmetic unit. xab x space address bus. xdb x space data bus. yaau y space address arithmetic unit. yab y space address bus. ydb y space data bus. ybase direct addressing base register. y dau register (16-bit halves specified as y, yl).
data sheet dsp1627 digital signal processor march 2000 14 lucent technologies inc. 4 hardware architecture (continued) interruptibility vectored interrupts are serviced only after the execution of an interruptible instruction. if more than one vectored interrupt is asserted at the same time, the interrupts are serviced sequentially according to their assigned priori- ties. see table 4 for the priorities assigned to the vec- tored interrupts. interrupt service routines, branch and conditional branch instructions, cache loops, and in- structions that only decrement one of the ram pointers, r0 to r3 (e.g., *r3 - - ), are not interruptible. a trap is similar to an interrupt, but it gains control of the processor by branching to the trap service routine even when the current instruction is noninterruptible. it may not be possible to return to normal instruction execution from the trap service routine since the machine state cannot always be saved. in particular, program execu- tion cannot be continued from a trapped cache loop or interrupt service routine. while in a trap service routine, another trap is ignored. when set to 1, the status bits in the ins register indicate that an interrupt has occurred. the processor must reach an interruptible state (completion of an interrupt- ible instruction) before an enabled vectored interrupt will be acted on. an interrupt will not be serviced if it is not enabled. polled interrupt service can be implemented by disabling the interrupt in the inc register and then polling the ins register for the expected event. vectored interrupts tables 29 and 30 show the inc and ins registers. a logic 1 written to any bit of inc enables (or unmasks) the as- sociated interrupt. if the bit is cleared to a logic 0, the in- terrupt is masked. note that neither the software interrupt nor traps can be masked. the occurrence of an interrupt that is not masked will cause the program execution to transfer to the memory location pointed to by that interrupt's vector address, as- suming no other interrupt is being serviced (see table 4, interrupt vector table). the occurrence of an inter- rupt that is masked causes no automatic processor ac- tion, but will set the corresponding status bit in the ins register. if a masked interrupt occurs, it is latched in the ins register, but the interrupt is not taken. when un- latched, this latched interrupt will initiate automatic pro- cessor interrupt action. see the dsp1611/17/18/27 digital signal processor information manual for a more detailed description of the interrupts. signaling interrupt service status five pins of dsp1627 are devoted to signaling interrupt service status. the iack pin goes high while any inter- rupt or user trap is being serviced, and goes low when the ireturn instruction from the service routine is issued. four pins, vec[3:0], carry a code indicating which of the interrupts or trap is being serviced. table 4 contains the encodings used by each interrupt. traps due to hds breakpoints have no effect on either the iack or vec[3:0] pins. instead, they show the inter- rupt state or interrupt source of the dsp when the trap occurred. clearing interrupts the phif interrupts (pibf and pobe) are cleared by reading or writing the parallel host interface data trans- mit registers pdx0[in] and pdx0[out], respectively. the sio and sio2 interrupts (ibf, ibf2, obe, and obe2) are cleared by reading or writing, as appropriate, the se- rial data registers sdx[in], sdx2[in], sdx[out], and sdx2[out]. the jtag interrupt (jint) is cleared by read- ing the jtag register. three of the vectored interrupts are cleared by writing to the ins register. writing a 1 to the int0, int1, or time bits in the ins will cause the corresponding interrupt sta- tus bit to be cleared to a logic 0. the status bit for these vectored interrupts is also cleared when the ireturn in- struction is executed, leaving set any other vectored in- terrupts that are pending. traps the trap pin of the dsp1627 is a bidirectional signal. at reset, it is configured as an input to the processor. asserting the trap pin will force a user trap. the trap mechanism is used for two purposes. it can be used by an application to rapidly gain control of the processor for asynchronous time-critical event handling (typically for catastrophic error recovery). it is also used by the hds for breakpointing and gaining control of the processor. separate vectors are provided for the user trap (0x46) and the hds trap (0x3). traps are not maskable.
data sheet march 2000 dsp1627 digital signal processor lucent technologies inc. 15 4 hardware architecture (continued) table 4. interrupt vector table source vector priority vec[3:0] issued by no interrupt 0x0 software interrupt 0x2 1 0x1 icall int0 0x1 2 0x2 pin jint 0x42 3 0x8 jtag in int1 0x4 4 0x9 pin time 0x10 7 0xc timer ibf2 0x14 8 0xd sio2 in obe2 0x18 9 0xe sio2 out reserved 0x1c 10 0x0 reserved 0x20 11 0x1 reserved 0x24 12 0x2 ibf 0x2c 14 0x3 sio in obe 0x30 15 0x4 sio out pibf 0x34 16 0x5 phif in pobe 0x38 17 0x6 phif out trap from hds 0x3 18 * * traps due to hds breakpoints have no effect on vec[3:0] pins. breakpoint, jtag, or pin trap from user 0x46 19 = highest 0x7 pin a trap has four cycles of latency. at most, two instruc- tions will execute from the time the trap is received at the pin to when it gains control. an instruction that is ex- ecuting when a trap occurs is allowed to complete be- fore the trap service routine is entered. (note that the instruction could be lengthened by wait-states.) during normal program execution, the pi register contains ei- ther the address of the next instruction (two-cycle in- struction executing) or the address following the next instruction (one-cycle instruction executing). in an inter- rupt service routine, pi contains the interrupt return ad- dress. when a trap occurs during an interrupt service routine, the value of the pi register may be overwritten. specifically, it is not possible to return to an interrupt service routine from a user trap (0x46) service routine. continuing program execution when a trap occurs dur- ing a cache loop is also not possible. the hds trap causes circuitry to force the program memory map to map1 (with on-chip rom starting at ad- dress 0x0) when the trap is taken. the previous memo- ry map is restored when the trap service routine exits by issuing an ireturn. the map is forced to map1 because the hds code, if present, resides in the on-chip rom. using the lucent technologies development tools, the trap pin may be configured to be an output, or an input vectoring to address 0x3. in a multiprocessor environ- ment, the trap pins of all the dsps present can be tied together. during hds operations, one dsp is selected by the host software to be the master. the master pro- cessor's trap pin is configured to be an output. the trap pins of the slave processors are configured as inputs. when the master processor reaches a break- point, the master's trap pin is asserted. the slave pro- cessors will respond to their trap input by beginning to execute the hds code. await interrupt (standby or sleep mode) setting the await bit (bit 15) of the alf register (alf = 0x8000) causes the processor to go into a power- saving standby or sleep mode. only the minimum cir- cuitry on the chip required to process an incoming inter- rupt remains active. after the await bit is set, one additional instruction will be executed before the stand- by power-saving mode is entered. a phif or sio word transfer will complete if already in progress. the await bit is reset when the first interrupt occurs. the chip then wakes up and continues executing. two nop instructions should be programmed after the await bit is set. the first nop (one cycle) will be exe- cuted before sleeping; the second will be executed after the interrupt signal awakens the dsp and before the in- terrupt service routine is executed. the await bit should be set from within the cache if the code which is executing resides in external rom where more than one wait-state has been programmed. this ensures that an interrupt will not disturb the device from completely entering the sleep state.
data sheet dsp1627 digital signal processor march 2000 16 lucent technologies inc. 4 hardware architecture (continued) for additional power savings, set ioc = 0x0180 and tim- erc = 0x0040 in addition to setting alf = 0x8000. this will hold the cko pin low and shut down the timer and pres- caler (see table 38 and table 31). for a description of the control mechanisms for putting the dsp into low-power modes, see section 4.13, pow- er management. 4.4 memory maps and wait-states the dsp1600 core implements a modified harvard ar- chitecture that has separate on-chip 16-bit address and data buses for the instruction/coefficient (x) and data (y) memory spaces. table 5 shows the instruction/coef- ficient memory space maps for both the dsp1627x36 and dsp1627x32. the differences between the x36 and x32 memory maps can be seen by comparing the respective map1 and map3. for instance, map1 of the x36 provides for 36 kwords of irom and 6 kwords of dual-port ram (dpram), whereas map1 of the x32 provides for 32 kwords of irom, 6 kwords of dpram, and 16 kwords of erom. the dsp1627 provides a multiplexed external bus which accesses external ram (eram) and rom (er- om). programmable wait-states are provided for exter- nal memory accesses. the instruction/coefficient memory map is configurable to provide application flex- ibility. table 6 shows the data memory space, which has one map. instruction/coefficient memory map selection in determining which memory map to use, the proces- sor evaluates the state of two parameters. the first is the lowpr bit (bit 14) of the alf register. the lowpr bit of the alf register is initialized to 0 automatically at re- set. lowpr controls the starting address in memory assigned to the six 1k banks of dual-port ram. if low- pr is low, internal dual-port ram begins at address 0xc000. if lowpr is high, internal dual-port ram be- gins at address 0x0. lowpr also moves irom from 0x0 in map1 to 0x4000 in map3, and erom from 0x0 in map2 to 0x4000 in map4. the second parameter is the value at reset of the exm pin (pin 27 or pin 14, depending upon the package type). exm determines whether the internal 36 kwords rom (irom) will be addressable in the memory map. the lucent technologies development system tools, together with the on-chip hds circuitry and the jtag port, can independently set the memory map. specifi- cally, during an hds trap, the memory map is forced to map1. the user's map selection is restored when the trap service routine has completed execution. map1 map1 has the irom starting at 0x0 and six 1 kword banks of dpram starting at 0xc000. additionally, map1 for the x32 has 16 kwords of erom starting at 0x8000. map1 is used if dsp1627 has exm low at re- set and the lowpr parameter is programmed to zero. it is also used during an hds trap. map2 map2 differs from map1 in that the lowest 48 kwords reference external rom (erom). map2 is used if exm is high at reset, the lowpr parameter is programmed to zero, and an hds trap is not in progress. map3 map3 has the six 1 kword banks of dpram starting at address 0x0. in map3 of the x36, the 36 kwords of irom start at 0x4000. similarly, for the x32, 32 kwords of irom start at 0x4000. additionally, map3 for the x32 has 16 kwords of erom starting at 0xc000. map3 is used if exm is low at reset, the lowpr bit is pro- grammed to 1, and an hds trap is not in progress. note that this map is not available if the secure mask-pro- grammable option has been ordered. map4 map4 differs from map3 in that addresses above 0x4000 reference external rom (erom). this map is used if the lowpr bit is programmed to 1, an hds trap is not in progress, and, either exm is high during reset, or the secure mask-programmable option has been or- dered. whenever the chip is reset using the rstb pin, the de- fault memory map will be map1 or map2, depending upon the state of the exm pin at reset. a reset through the hds will not reinitialize the alf register, so the previ- ous memory map is retained. boot from external rom after rstb goes from low to high, the dsp1627 comes out of reset and fetches an instruction from address zero of the instruction/coefficient space. the physical location of address zero is determined by the memory map in effect. if exm is high at the rising edge of rstb, map2 is selected. map2 has erom at location zero; thus, program execution begins from external memory. if exm is high and int1 is low when rstb rises, the mwait register defaults to 15 wait-states for all external memory segments. if int1 is high, the mwait register defaults to 0 wait-states.
data sheet march 2000 dsp1627 digital signal processor lucent technologies inc. 17 4 hardware architecture (continued) table 5. instruction/coefficient memory maps * map1 is set automatically during an hds trap. the user-selected map is restored at the end of the hds trap service routine. ? lowpr is an alf register bit. the lucent technologies development system tools can independently set the memory map. ? map3 is not available if the secure mask-programmable option is selected. * map1 is set automatically during an hds trap. the user-selected map is restored at the end of the hds trap service routine. ? lowpr is an alf register bit. the lucent technologies development system tools can independently set the memory map. ? map3 is not available if the secure mask-programmable option is selected. dsp1627x36 x address ab[0:15] map 1 * exm = 0 lowpr = 0 ? map 2 exm = 1 lowpr = 0 map 3 ? exm = 0 lowpr = 1 map 4 exm = 1 lowpr = 1 00x0000 irom (36k) erom (48k) dpram (6k) dpram (6k) 4k 0x1000 6k 0x1800 reserved (10k) reserved (10k) 12k 0x3000 16k 0x4000 irom (36k) erom (48k) 20k 0x5000 24k 0x6000 28k 0x7000 32k 0x8000 36k 0x9000 reserved (12k) 40k 0xa000 44k 0xb000 48k 0xc000 dpram (6k) dpram (6k) 52k 0xd000 reserved (12k) 54k 0xd800 reserved (10k) reserved (10k) 56k 0xe000 60k64k 0xffff dsp1627x32 x address ab[0:15] map 1 * exm = 0 lowpr = 0 ? map 2 exm = 1 lowpr = 0 map 3 ? exm = 0 lowpr = 1 map 4 exm = 1 lowpr = 1 0 0x0000 irom (32k) erom (48k) dpram (6k) dpram (6k) 4k 0x1000 6k 0x1800 reserved (10k) reserved (10k) 12k 0x3000 16k 0x4000 irom (32k) erom (48k) 20k 0x5000 24k 0x6000 28k 0x7000 32k 0x8000 erom (16k) 36k 0x9000 40k 0xa000 44k 0xb000 48k 0xc000 dpram (6k) dpram (6k) erom (16k) 52k 0xd000 54k 0xd800 reserved (10k) reserved (10k) 56k 0xe000 60k64k 0xffff
data sheet dsp1627 digital signal processor march 2000 18 lucent technologies inc. 4 hardware architecture (continued) data memory mapping on the data memory side (see table 6), the six 1k banks of dual-port ram are located starting at address 0. addresses from 0x4000 to 0x40ff reference a 256- word memory-mapped i/o segment (io). addresses from 0x4100 to 0x7fff reference the low external data ram segment (eramlo). addresses above 0x8000 reference high external data ram (eramhi). wait-states the number of wait-states (from 0 to 15) used when ac- cessing each of the four external memory segments (eramlo, io, eramhi, and erom) is programmable in the mwait register (see table 36). when the program references memory in one of the four external seg- ments, the internal multiplexer is automatically switched to the appropriate set of internal buses, and the associ- ated external enable of eramlo, io, eramhi, or erom is issued. the external memory cycle is auto- matically stretched by the number of wait-states config- ured in the appropriate field of the mwait register. 4.5 external memory interface (emi) the external memory interface supports read/write op- erations from instruction/coefficient memory, data memory, and memory-mapped i/o devices. the dsp1627 provides a 16-bit external address bus, ab[15:0], and a 16-bit external data bus, db[15:0]. these buses are multiplexed between the internal bus- es for the instruction/coefficient memory and the data memory. four external memory segment enables, eramlo, io, eramhi, and erom, select the external memory segment to be addressed. if a data memory location with an address between 0x4100 and 0x7fff is addressed, eramlo is asserted low. if one of the 256 external data memory locations, with an address greater than or equal to 0x4000, and less than or equal to 0x40ff, is addressed, io is asserted low. io is intended for memory-mapped i/o. if a data memory location with an address greater than or equal to 0x8000 is addressed, eramhi is asserted low. when the external instruction/coefficient memory is addressed, erom is asserted low. the flexibility provided by the programmable options of the external memory interface (see table 36, mwait register and table 38, ioc register) allows the dsp1627 to interface gluelessly with a variety of com- mercial memory chips. each of the four external memory segments, eramlo, io, eramhi, and erom, has a number of wait-states that is programmable (from 0 to 15) by writing to the mwait register. when the program references memory in one of the four external segments, the internal multi- plexer is automatically switched to the appropriate set of internal buses, and the associated external enable of eramlo, io, eramhi, or erom is issued. the exter- nal memory cycle is automatically stretched by the num- ber of wait-states in the appropriate field of the mwait register. when writing to external memory, the rwn pin goes low for the external cycle. the external data bus, db[15:0], is driven by the dsp1627 starting halfway through the cycle. the data driven on the external data bus is automatically held after the cycle unless an exter- nal read cycle immediately follows. the dsp1627 has one external address bus and one external data bus for both memory spaces. since some instructions provide the capability of simultaneous ac- cess to both x space and y space, some provision must be made to avoid collisions for external accesses. the dsp1627 has a sequencer that does the external x ac- cess first, and then the external y access, transparently to the programmer. wait-states are maintained as table 6. data memory map (not to scale) decimal address address in r0, r1, r2, r3 segment 0 0x0000 dpram[1:6] 6k 0x1800 reserved (10k) 16k 0x4000 io 16,640 0x4100 eramlo 32k 0x8000 eramhi 64k C 1 0xffff
data sheet march 2000 dsp1627 digital signal processor lucent technologies inc. 19 4 hardware architecture (continued) programmed in the mwait register. for example, let two instructions be executed: the first reads a coefficient from erom and writes data to eram; the second reads a coefficient from erom and reads data from eram. the sequencer carries out the following steps at the ex- ternal memory interface: read erom, write eram, read erom, and read eram. each step is done in sequen- tial one-instruction cycle steps, assuming zero wait- states are programmed. note that the number of in- struction cycles taken by the two instructions is four. al- so, in this case, the write hold time is zero. the dsp1627 allows writing into external instruction/ coefficient memory. by setting bit 11, werom, of the ioc register (see table 38), writing to (or reading from) data memory or memory-mapped i/o asserts the erom strobe instead of eramlo, io, or eramhi. therefore, with werom set, erom appears in both y space (replacing eram) and x space, in its normal po- sition. bit 14 of the ioc register (see table 38), extrom, may be used with werom to download to a full 64k of ex- ternal memory. when werom and extrom are both asserted, address bit 15 (ab15) is held low, aliasing the upper 32k of external memory into the lower 32k. when an access to internal memory is made, the ab[15:0] bus holds the last valid external memory ad- dress. asserting the rstb pin low 3-states the ab[15:0] bus. after reset, the ab[15:0] value is undefined. the leading edge of the memory segment enables can be delayed by approximately one-half a cko period by programming the ioc register (see table 38). this is used to avoid a situation in which two devices drive the data bus simultaneously. bits 7, 8, and 13 of the ioc register select the mode of operation for the cko pin (see table 38). available op- tions are a free-running unstretched clock, a wait-stated sequenced clock (runs through two complete cycles during a sequenced external memory access), and a wait-stated clock based on the internal instruction cycle. these clocks drop to the low-speed internal ring oscilla- tor when slowcki is enabled (see 4.13, power man- agement). the high-to-low transitions of the wait-stated clock are synchronized to the high-to-low transition of the free-running clock. also, the cko pin provides ei- ther a continuously high level, a continuously low level, or changes at the rate of the internal processor clock. this last option, only available with the crystal and small-signal input clock options, enables the dsp1627 cki input buffer to deliver a full-rate clock to other devic- es while the dsp1627 itself is in one of the low-power modes. 4.6 bit manipulation unit (bmu) the bmu interfaces directly to the main accumulators in the dau providing the following features: n barrel shiftinglogical and arithmetic, left and right shift n normalization and extraction of exponent n bit-field extraction and insertion these features increase the efficiency of the dsp in ap- plications such as control or data encoding and decod- ing. for example, data packing and unpacking, in which short data words are packed into one 16-bit word for more efficient memory storage, is very easy. in addition, the bmu provides two auxiliary accumula- tors, aa0 and aa1. in one instruction cycle, 36-bit data can be shuffled, or swapped, between one of the main accumulators and one of the alternate accumulators. the ar<03> registers are 16-bit registers that control the operations of the bmu. they store a value that de- termines the amount of shift or the width and offset fields for bit extraction or insertion. certain operations in the bmu set flags in the dau psw register and the alf register (see table 26, processor status word (psw) register, and table 35, alf register). the ar<03> reg- isters can also be used as general-purpose registers. the bmu instructions are detailed in section 5.1. for a thorough description of the bmu, see the dsp1611/17/ 18/27 digital signal processor information manual . 4.7 serial i/o units (sios) the serial i/o ports on the dsp1627 device provide a serial interface to many codecs and signal processors with little, if any, external hardware required. each high- speed, double-buffered port (sdx and sdx2) supports back-to-back transmissions of data. sio and sio2 are identical. the output buffer empty (obe and obe2) and input buffer full (ibf and ibf2) flags facilitate the read- ing and/or writing of each serial i/o port by program- or interrupt-driven i/o. there are four selectable active clock speeds. a bit-reversal mode provides compatibility with either the most significant bit (msb) first or least significant bit (lsb) first serial i/o formats (see table 22, serial i/o control registers (sioc and sioc2)). a multiprocessor i/o configuration is supported. this feature allows up to eight dsp161x devices to be connected together on an sio port without requiring external glue logic.
data sheet dsp1627 digital signal processor march 2000 20 lucent technologies inc. 4 hardware architecture (continued) the serial data may be internally looped back by setting the sio loopback control bit, siolbc, of the ioc regis- ter. siolbc affects both the sio and sio2. the data output signals are wrapped around internally from the output to the input (do1 to di1 and do2 to di2). to ex- ercise loopback, the sio clocks (ick1, ick2, ock1, and ock2) should either all be in the active mode, 16-bit condition, or each pair should be driven from one external source in passive mode. similarly, pins ild1 (ild2) and old1 (old2) must both be in active mode or tied together and driven from one external frame clock in passive mode. during loopback, do1, do2, di1, di2, ick1, ick2, ock1, ock2, ild1, ild2, old1, old2, sadd1, sadd2, sync1, sync2, doen1, and doen2 are 3-stated. setting dodly = 1 (sioc and sioc2) delays do by one phase of ock so that do changes on the falling edge of ock instead of the rising edge (dodly = 0). this re- duces the time available for do to drive di and to be val- id for the rising edge of ick, but increases the hold time on do by half a cycle on ock. programmable modes programmable modes of operation for the sio and sio2 are controlled by the serial i/o control registers (sioc and sioc2). these registers, shown in table 22, are used to set the ports into various configurations. both input and output operations can be independently configured as either active or passive. when active, the dsp1627 generates load and clock signals. when pas- sive, load and clock signal pins are inputs. since input and output can be independently config- ured, each sio has four different modes of operation. each of the sioc registers is also used to select the fre- quency of active clocks for that sio. finally, these reg- isters are used to configure the serial i/o data formats. the data can be 8 or 16 bits long, and can also be input/ output msb first or lsb first. input and output data for- mats can be independently configured. multiprocessor mode the multiprocessor mode allows up to eight processors (dsp1629, dsp1628, dsp1627, dsp1620, dsp1618, dsp1617, dsp1616, dsp1611) to be connected to- gether to provide data transmission among any of the dsps in the system. either sio port (sio or sio2) may be independently used for the multiprocessor mode. the multiprocessor interface is a four-wire interface, consisting of a data channel, an address/protocol channel, a transmit/receive clock, and a sync signal (see figure 5). the di1 and do1 pins of all the dsps are connected to transmit and receive the data channel. the sadd1 pins of all the dsps are connected to trans- mit and receive the address/protocol channel. ick1 and ock1 should be tied together and driven from one source. the sync1 pins of all the dsps are connected. in the configuration shown in figure 5, the master dsp (dsp0) generates active sync1 and ock1 signals while the slave dsps use the sync1 and ock1 signals in passive mode to synchronize operations. in addition, all dsps must have their ild1 and old1 signals in ac- tive mode. while ild1 and old1 are not required externally for multiprocessor operation, they are used internally in the dsp's sio. setting the ld field of the master's sioc reg- ister to a logic level 1 will ensure that the active genera- tion of sync1, ild1, and old1 is derived from ock1 (see table 22). with this configuration, all dsps should use ick1 (tied to ock1) in passive mode to avoid con- flicts on the clock (ck) line (see the dsp1611/17/18/27 digital signal processor information manual for more information). four registers (per sio) configure the multiprocessor mode: the time-division multiplexed slot register (tdms or tdms2), the serial receive and transmit address reg- ister (srta or srta2), the serial data transmit register (sdx or sdx2), and the multiprocessor serial address/protocol register (saddx or saddx2). multiprocessor mode requires no external logic and uses a tdm interface with eight 16-bit time slots per frame. the transmission in any time slot consists of 16 bits of serial data in the data channel and 16 bits of address and protocol information in the address/proto- col channel. the address information consists of the transmit address field of the srta register of the transmit- ting device. the address information is transmitted con- currently with the transmission of the first 8 bits of data. the protocol information consists of the transmit proto- col field written to the saddx register and is transmitted concurrently with the last 8 bits of data (see table 25, multiprocessor protocol register). data is received or recognized by other dsp(s) whose receive address matches the address in the address/protocol channel. each sio port has a user-programmable receive ad- dress and transmit address associated with it. the transmit and receive addresses are programmed in the srta register. in multiprocessor mode, each device can send data in a unique time slot designated by the tdms register trans- mit slot field (bits 70). the tdms register has a fully de- coded transmit slot field in order to allow one dsp1627 device to transmit in more than one time slot. this pro- cedure is useful for multiprocessor systems with less than eight dsp1627 devices when a higher bandwidth is necessary between certain devices in that system. the dsp operating during time slot 0 also drives sync1.
data sheet march 2000 dsp1627 digital signal processor lucent technologies inc. 21 4 hardware architecture (continued) in order to prevent multiple bus drivers, only one dsp can be programmed to transmit in a particular time slot. in addition, it is important to note that the address/pro- tocol channel is 3-stated in any time slot that is not being driven. therefore, to prevent spurious inputs, the address/pro- tocol channel should be pulled up to v dd with a 5 k w re- sistor, or it should be guaranteed that the bus is driven in every time slot. (if the sync1 signal is externally gen- erated, then this pull-up is required for correct initializa- tion.) each sio also has a fully decoded transmitting address specified by the srta register transmit address field (bits 70). this is used to transmit information regarding the destination(s) of the data. the fully decoded receive ad- dress specified by the srta register receive address field (bits 158) determines which data will be received. the sio protocol channel data is controlled via the sad- dx register. when the saddx register is written, the lower 8 bits contain the 8-bit protocol field. on a read, the high-order 8 bits read from saddx are the most re- cently received protocol field sent from the transmitting dsp's saddx output register. the low-order 8 bits are read as 0s. an example use of the protocol channel is to use the top 3 bits of the saddx value as an encoded source address for the dsps on the multiprocessor bus. this leaves the remaining 5 bits available to convey additional control information, such as whether the associated field is an opcode or data, or whether it is the last word in a trans- fer, etc. these bits can also be used to transfer parity in- formation about the data. alternatively, the entire field can be used for data transmission, boosting the band- width of the port by 50%. using sio2 the sio2 functions the same as the sio. please refer to pin multiplexing in section 4.1 for a description of pin multiplexing of bio, phif, vec[3:0], and sio2. figure 5. multiprocessor communication and connections dsp 0 do ick sadd sync dsp 1 dsp 7 data channel clock address/protocol channel sync signal di ock do ick sadd sync di ock do ick sadd sync di ock 5 k w v dd 5-4181 (f).a
data sheet dsp1627 digital signal processor march 2000 22 lucent technologies inc. 4 hardware architecture (continued) 4.8 parallel host interface (phif) the dsp1627 has an 8-bit parallel host interface for rap- id transfer of data with external devices. this parallel port is passive (data strobes provided by an external device) and supports either motorola or intel microcontroller pro- tocols. the phif also provides for 8-bit or 16-bit data transfers. as a flexible host interface, it requires little or no glue logic to interface to other devices (e.g., microcon- trollers, microprocessors, or another dsp). the data path of the phif consists of a 16-bit input buff- er, pdx0 (in), and a 16-bit output buffer, pdx0 (out). two output pins, parallel input buffer full (pibf) and parallel output buffer empty (pobe), indicate the state of the buffers. in addition, there are two registers used to con- trol and monitor the phif's operation: the parallel host in- terface control register ( phifc , see table 28), and the phif status register (pstat, see table 8). the pstat register, which reflects the state of the pibf and pobe flags, can only be read by an external device when the pstat input pin is asserted. the phifc register defines the programmable options for this port. the function of the pins, pids and pods, is programma- ble to support both the intel and motorola protocols. the pin, pcsn, is an input that, when low, enables pids and pods (or prwn and pds, depending on the protocol used). while pcsn is high, the dsp1627 ignores any ac- tivity on pids and/or pods. if a dsp1627 is intended to be continuously accessed through the phif port, pcsn should be grounded. if pcsn is low and their respective bits in the inc register are set, the assertion of pids and pods by an external device causes the dsp1627 de- vice to recognize an interrupt. programmability the parallel host interface can be programmed for 8-bit or 16-bit data transfers using bit 0, pmode, of the phifc register. setting pmode selects 16-bit transfer mode. an input pin controlled by the host, pbsel, determines an access of either the high or low bytes. the assertion level of the pbsel input pin is configurable in software using bit 3 of the phifc register, pbself. table 7 sum- marizes the port's functionality as controlled by the pstat and pbsel pins and the pbself and pmode fields. for 16-bit transfers, if pbself is zero, the pibf and pobe flags are set after the high byte is transferred. if pbself is one, the flags are set after the low byte is transferred. in 8-bit mode, only the low byte is accessed, and every completion of an input or output access sets pibf or pobe. bit 1 of the phifc register, pstrobe, configures the port to operate either with an intel protocol where only the chip select (pcsn) and either of the data strobes (pids or pods) are needed to make an access, or with a mo- torola protocol where the chip select (pcsn), a data strobe (pds), and a read/write strobe (prwn) are need- ed. pids and pods are negative assertion data strobes while the assertion level of pds is programmable through bit 2, pstrb, of the phifc register. finally, the assertion level of the output pins, pibf and pobe, is controlled through bit 4, pflag. when pflag is set low, pibf and pobe output pins have positive as- sertion levels. by setting bit 5, pflagsel, the logical or of pibf and pobe flags (positive assertion) is seen at the output pin pibf. by setting bit 7 in phifc , psobef, the polarity of the pobe flag in the status register, pstat, can be changed. psobef has no effect on the pobe pin. pin multiplexing please refer to pin multiplexing in section 4.1 for a de- scription of bio, phif, vec[3:0], and sio2 pins. table 7. phif function (8-bit and 16-bit modes) pmode field pstat pin pbsel pin pbself field = 0 pbself field = 1 0 (8-bit) 0 0 pdx0 low byte reserved 0 0 1 reserved pdx0 low byte 010pstatreserved 0 1 1 reserved pstat 1 (16-bit) 0 0 pdx0 low byte pdx0 high byte 1 0 1 pdx0 high byte pdx0 low byte 110pstatreserved 1 1 1 reserved pstat table 8. pstat register as seen on pb[7:0] bit 76543 2 1 0 field reserved pibf pobe
data sheet march 2000 dsp1627 digital signal processor lucent technologies inc. 23 4 hardware architecture (continued) 4.9 bit input/output unit (bio) the bio controls the directions of eight bidirectional con- trol i/o pins, iobit[7:0]. if a pin is configured as an output, it can be individually set, cleared, or toggled. if a pin is configured as an input, it can be read and/or tested. the lower half of the sbit register (see table 33) contains current values (value[7:0]) of the eight bidirectional pins iobit[7:0]. the upper half of the sbit register (di- rec[7:0]) controls the direction of each of the pins. a log- ic 1 configures the corresponding pin as an output; a logic 0 configures it as an input. the upper half of the sbit reg- ister is cleared upon reset. the cbit register (see table 34) contains two 8-bit fields, mode/mask[7:0] and data/pat[7:0]. the values of data/pat[7:0] are cleared upon reset. the meaning of a bit in either field depends on whether it has been config- ured as an input or an output in sbit . if a pin has been con- figured to be an output, the meanings are mode and data. for an input, the meanings are mask and pat (pattern). table 9 shows the functionality of the mode/ mask and data/pat bits based on the direction select- ed for the associated iobit pin. those bits that have been configured as inputs can be in- dividually tested for 1 or 0. for those inputs that are being tested, there are four flags produced: allt (all true), allf (all false), somet (some true), and somef (some false). these flags can be used for conditional branch or special in- structions. the state of these flags can be saved and re- stored by reading and writing bits 0 to 3 of the alf register (see table 35). if a bio pin is switched from being configured as an out- put to being configured as an input and then back to be- ing configured as an output, the pin retains the previous output value. pin multiplexing please refer to pin multiplexing in section 4.1 for a description of bio, phif, vec[3:0], and sio2 pins. 4.10 timer the interrupt timer is composed of the timerc (control) register, the timer0 register, the prescaler, and the counter itself. the timer control register (see table 31, timerc register) sets up the operational state of the timer and prescaler. the timer0 register is used to hold the counter reload value (or period register) and to set the initial value of the counter. the prescaler slows the clock to the timer by a number of binary divisors to allow for a wide range of interrupt delay periods. the counter is a 16-bit down counter that can be loaded with an arbitrary number from software. it counts down to 0 at the clock rate provided by the prescaler. upon reaching 0 count, a vectored interrupt to program ad- dress 0x10 is issued to the dsp1627, providing the in- terrupt is enabled (bit 8 of inc and ins registers). the counter will then either wait in an inactive state for anoth- er command from software, or will automatically repeat the last interrupting period, depending upon the state of the reload bit in the timerc register. when reload is 0, the counter counts down from its initial value to 0, interrupts the dsp1627, and then stops, remaining inactive until another value is written to the timer0 register. writing to the timer0 register causes both the counter and the period register to be written with the specified 16-bit number. when reload is 1, the counter counts down from its initial value to 0, interrupts the dsp1627, automatically reloads the specified initial value from the period register into the counter, and re- peats indefinitely. this provides for either a single timed interrupt event or a regular interrupt clock of arbitrary pe- riod. the timer can be stopped and started by software, and can be reloaded with a new period at any time. its count value, at the time of the read, can also be read by soft- ware. due to pipeline stages, stopping and starting the timer may result in one inaccurate count or prescaled pe- riod. when the dsp1627 is reset, the bottom 6 bits of the timerc register and the timer0 register and counter are initialized to 0. this sets the prescaler to cko/2*, turns off the reload feature, disables timer counting, and initial- izes the timer to its inactive state. the act of resetting the chip does not cause a timer interrupt. note that the peri- od register is not initialized on reset. the t0en bit of the timerc register enables the clock to the timer. when t0en is a 1, the timer counts down to- wards 0. when t0en is a 0, the timer holds its current count. * frequency of cko/2 is equivalent to either cki/2 for the pll by- passed or related to cki by the pll multiplying factors. see section 4.12, clock synthesis. table 9. bio operations direc[n] * *0 n 7. mode/ mask[n] data/ pat[n] action 1 (output) 0 0 clear 1 (output) 0 1 set 1 (output) 1 0 no change 1 (output) 1 1 toggle 0 (input) 0 0 no test 0 (input) 0 1 no test 0 (input) 1 0 test for zero 0 (input) 1 1 test for one
data sheet dsp1627 digital signal processor march 2000 24 lucent technologies inc. 4 hardware architecture (continued) the prescale field of the timerc register selects one of 16 possible clock rates for the timer input clock (see table 31, timerc register). setting the disable bit of the timerc register to a logic 1 shuts down the timer and the prescaler for power sav- ings. setting the timerdis, bit 4, in the powerc register has the same effect of shutting down the timer. the disable bit and the timerdis bit are cleared by writ- ing a 0 to their respective registers to restore the normal operating mode. 4.11 jtag test port the dsp1627 uses a jtag/ ieee 1149.1 standard four- wire test port for self-test and hardware emulation. there is no separate trst input pin. an instruction reg- ister, a boundary-scan register, a bypass register, and a device identification register have been implemented. the device identification register coding for the dsp1627 is shown in table 37. the instruction register (ir) is 4 bits long. the instruction for accessing the de- vice id is 0xe (1110). the behavior of the instruction register is summarized in table 10. cell 0 is the lsb (closest to tdo). the first line shows the cells in the ir that capture from a parallel input in the capture-ir controller state. the second line shows the cells that always load a logic 1 in the capture-ir controller state. the third line shows the cells that always load a logic 0 in the capture-ir control- ler state. cell 3 (msb of ir) is tied to status signal pint, and cell 2 is tied to status signal jint. the state of these signals can therefore be captured during capture-ir and shifted out during shift-ir controller states. boundary-scan register all of the chip's inputs and outputs are incorporated in a jtag scan path shown in table 11. the types of boundary-scan cells are as follows: n i = input cell n o = 3-state output cell n b = bidirectional (i/o) cell n oe = 3-state control cell n dc = bidirectional control cell table 10. jtag instruction register ir cell #: 3 2 1 0 parallel input? y y n n always logic 1? n n n y always logic 0? n n y n
data sheet march 2000 dsp1627 digital signal processor lucent technologies inc. 25 4 hardware architecture (continued) note that the direction of shifting is from tdi to cell 104 to cell 103 . . . to cell 0 of tdo. * please refer to pin multiplexing in section 4.1 for a description of pin multiplexing of bio, phif, vec[3:0], and sio2. ? note that shifting a zero into this cell in the mode to scan a zero into the chip will disable the processor clocks just as th e stop pin will. ? when the jtag sample instruction is used, this cell will have a logic one regardless of the state of the pin. table 11. jtag boundary-scan register cell type signal name/function cell type signal name/function 0 oe controls cells 1, 2731 69 b ock2/pcsn* 1 o cko 70 dc controls cell 71 2irstb 71bdo2/pstat* 3 dc controls cell 4 72 dc controls cell 73 4 b trap 73 b sync2/pbsel* 5i stop ? 74 dc controls cell 75 6 o iack 75 b ild2/pids* 7 i int0 76 dc controls cell 77 8 oe controls cells 6, 1025, 49, 50, 78, 79 77 b old2/pods* 9 i int1 78 o ibf2/pibf* 1025 o ab[0:15] 79 o obe2/pobe* 26 i exm 80 dc controls cell 81 27 o rwn 81 b ick2/pb0* 2831 o erom, eramlo, eramhi, io 82 dc controls cell 83 3236 b db[0:4] 83 b di2/pb1* 37 dc controls cells 3236, 3848 84 dc controls cell 85 3848 b db[5:15] 85 b doen2/pb2* 49 o obe1 86 dc controls cell 87 50 o ibf1 87 b sadd2/pb3* 51 i di1 88 dc controls cell 89 52 dc controls cell 53 89 b iobit0/pb4* 53 b ild1 90 dc controls cell 91 54 dc controls cell 55 91 b iobit1/pb5* 55 b ick1 92 dc controls cell 93 56 dc controls cell 57 93 b iobit2/pb6* 57 b ock1 94 dc controls cell 95 58 dc controls cell 59 95 b iobit3/pb7* 59 b old1 96 dc controls cell 97 60 oe controls cell 61 97 b vec3/iobit4* 61 o do1 98 dc controls cell 99 62 dc controls cell 63 99 b vec2/iobit5* 63 b sync1 100 dc controls cell 101 64 dc controls cell 65 101 b vec1/iobit6* 65 b sadd1 102 dc controls cell 103 66 dc controls cell 67 103 b vec0/iobit7* 67 b doen1 104 i cki ? 68 dc controls cell 69
data sheet dsp1627 digital signal processor march 2000 26 lucent technologies inc. 4 hardware architecture (continued) 4.12 clock synthesis figure 6. clock source block diagram powerc ring oscillator m u x 2 n phase detector charge pump vco vco clock f vco loop filter m lf[3:0] mbits[4:0] nbits[2:0] pll/synthesizer cki input clock lock (flag to indicate lock condition of pll) f cki f slow clock slowcki pllc pllen internal processor clock f internal clock pllsel f cki 5-4520 (f) the dsp1627 provides an on-chip, programmable clock synthesizer. figure 6 is the clock source diagram. the 1x cki input clock, the output of the synthesizer, or a slow internal ring oscillator can be used as the source for the internal dsp clock. the clock synthesizer is based on a phase-locked loop (pll), and the terms clock synthesizer and pll are used interchangeably. on powerup, cki is used as the clock source for the dsp. this clock is used to generate the internal proces- sor clocks and cko, where f cki = f cko . setting the ap- propriate bits in the pllc control register (described in table 32) will enable the clock synthesizer to become the clock source. the powerc register, which is dis- cussed in section 4.13, can override the selection to stop clocks or force the use of the slow clock for low- power operation. pll control signals the input to the pll comes from one of the three mask- programmable clock options: cmos, crystal, or small- signal. the pll cannot operate without an external in- put clock. to use the pll, the pll must first be allowed to stabi- lize and lock to the programmed frequency. after the pll has locked, the lock flag is set and the lock detect circuitry is disabled. the synthesizer can then be used as the clock source. setting the pllsel bit in the pllc register will switch sources from f cki to f vco /2 without glitching. it is important to note that the setting of the pllc register must be maintained. otherwise, the pll will seek the new set point. every time the pllc register is written, the lock flag is reset.
data sheet march 2000 dsp1627 digital signal processor lucent technologies inc. 27 4 hardware architecture (continued) the frequency of the pll output clock, f vco , is deter- mined by the values loaded into the 3-bit n divider and the 5-bit m divider. when the pll is selected and locked, the frequency of the internal processor clock is related to the frequency of cki by the following equa- tions: f vco = f cki * m/n f internal clock = f cko = f vco ? 2 the frequency of the vco, f vco , must fall within the range listed in table 63. also note that f vco must be at least twice f cki . the coding of the mbits and nbits is described as fol- lows: mbits = m - 2 if (n == 1) nbits = 0x7 else nbits = n - 2 where n ranges from 1 to 8 and m ranges from 2 to 20. the loop filter bits lf[3:0] should be programmed ac- cording to table 64. two other bits in the pllc register control the pll. clear- ing the pllen bit powers down the pll; setting this bit powers up the pll. clearing the pllsel bit deselects the pll so that the dsp is clocked by a 1x version of the cki input; setting the pllsel bit selects the pll- generated clock for the source of the dsp internal pro- cessor clock. the pllc register is cleared on reset and powerup. therefore, the dsp comes out of reset with the pll deselected and powered down. m and n should be changed only while the pll is deselected. the val- ues of m and n should not be changed when powering down or deselecting the pll. as previously mentioned, the pll also provides a user flag, lock, to indicate when the loop has locked. when this flag is not asserted, the pll output is unstable. the dsp should not be switched to the pll-based clock without first checking that the lock flag is set. the lock flag is cleared by writing to the pllc register. when the pll is deselected, it is necessary to wait for the pll to relock before the dsp can be switched to the pll- based clock. before the input clock is stopped, the pll should be powered down. otherwise, the lock flag will not be reset and there may be no way to determine if the pll is stable, once the input clock is applied again. the lock-in time depends on the frequency of operation and the values programmed for m and n (see table 64).
data sheet dsp1627 digital signal processor march 2000 28 lucent technologies inc. 4 hardware architecture (continued) pll programming examples the following section of code illustrates how the pll would be initialized on powerup, assuming the following oper- ating conditions: n cki input frequency = 10 mhz n internal clock and cko frequency = 50 mhz n vco frequency = 100 mhz n input divide down count n = 2 (set nbits[2:0] = 000 to get n = 2, as described in table 32.) n feedback down count m = 20 (set mbits[4:0] = 10010 to get m = 18 + 2 = 20, as described in table 32.) the device would come out of reset with the pll disabled and deselected. pllinit: pllc = 0x2912 /* running cki input clock at 10 mhz, set up counters in pll */ pllc = 0xa912 /* power on pll, but pll remains deselected */ call pllwait /* loop to check for lock flag assertion */ pllc = 0xe912 /* select high-speed, pll clock */ goto start /* user's code, now running at 50 mhz */ pllwait: if lock return goto pllwait programming examples which illustrate how to use the pll with the various power management modes are listed in section 4.13. latency the switch between the cki-based clock and the pll-based clock is synchronous. this method results in the actual switch taking place several cycles after the pllsel bit is changed. during this time, actual code can be executed, but it will be at the previous clock rate. table 12 shows the latency times for switching between cki-based and pll- based clocks. in the example given, the delay to switch to the pll source is 14 cko cycles and to switch back is 1131 cko cycles. frequency accuracy and jitter when using the pll to multiply the input clock frequency up to the instruction clock rate, it is important to realize that although the average frequency of the internal clock and cko will have about the same relative accuracy as the input clock, noise sources within the dsp will produce jitter on the pll clock such that each individual clock period will have some error associated with it. the pll is guaranteed only to have sufficiently low jitter to operate the dsp, and thus, this clock should not be used as an input to jitter-sensitive devices in the system. v dda and v ssa connections the pll has its own power and ground pins, v dda and v ssa . additional filtering should be provided for v dda in the form of a ferrite bead connected from v dda to v dd and two decoupling capacitors (4.7 m f tantalum in parallel with a 0.01 m f ceramic) from v dda to v ss . v ssa can be connected directly to the main ground plane. this recommen- dation is subject to change and may need to be modified for specific applications depending on the characteristics of the supply noise. note: for devices with the cmos clock input option, the cki2 pin should be connected to v ssa . table 12. latency times for switching between cki and pll-based clocks minimum latency (cycles) maximum latency (cycles) switch to pll-based clock 1 n + 2 switch from pll-based clock m/n + 1 m + m/n + 1
data sheet march 2000 dsp1627 digital signal processor lucent technologies inc. 29 4 hardware architecture (continued) 4.13 power management there are three different control mechanisms for putting the dsp1627 into low-power modes: the powerc control register, the stop pin, and the await bit in the alf reg- ister. the pll can also be disabled with the pllen bit of the pllc register for more power saving. powerc control register bits the powerc register has 10 bits that power down vari- ous portions of the chip and select the clock source: xtloff: assertion of the xtloff bit powers down the crystal oscillator or the small-signal input circuit, dis- abling the internal processor clock. assertion of the xtloff bit to disable the crystal oscillator also pre- vents its use as a noninverting buffer. since the oscilla- tor and the small-signal input circuits take many cycles to stabilize, care must be taken with the turn-on se- quence, as described later. slowcki: assertion of the slowcki bit selects the ring oscillator as the clock source for the internal pro- cessor clock instead of cki or the pll. when cki or the pll is selected, the ring oscillator is powered down. switching of the clocks is synchronized so that no par- tial or short clock pulses occur. two nop s should follow the instruction that sets or clears slowcki. nock: assertion of the nock bit synchronously turns off the internal processor clock, regardless of whether its source is provided by cki, the pll, or the ring oscil- lator. the nock bit can be cleared by resetting the chip with the rstb pin, or asserting the int0 or int1 pins. two nop s should follow the instruction that sets nock. the pll remains running, if enabled, while nock is set. int0en: this bit allows the int0 pin to asynchronously clear the nock bit, thereby allowing the device to con- tinue program execution from where it left off without any loss of state. no chip reset is required. it is recom- mended that, when int0en is to be used, the int0 interrupt be disabled in the inc register so that an unin- tended interrupt does not occur. after the program re- sumes, the int0 interrupt in the ins register should be cleared. int1en: this bit enables the int1 pin to be used as the nock clear, exactly like int0en previously described. the following control bits power down the peripheral i/o units of the dsp. these bits can be used to further reduce the power consumption during standard sleep mode. sio1dis: this is a powerdown signal to the sio1 i/o unit. it disables the clock input to the unit, thus eliminat- ing any sleep power associated with the sio1. since the gating of the clocks may result in incomplete trans- actions, it is recommended that this option be used in applications where the sio1 is not used or when reset may be used to reenable the sio1 unit. otherwise, the first transaction after reenabling the unit may be corrupt- ed. sio2dis: this bit powers down the sio2 in the same way sio1dis powers down the sio1. phifdis: this is a powerdown signal to the parallel host interface. it disables the clock input to the unit, thus eliminating any sleep power associated with the phif. since the gating of the clocks may result in incomplete transactions, it is recommended that this option be used in applications where the phif is not used, or when re- set may be used to reenable the phif. otherwise, the first transaction after reenabling the unit may be corrupt- ed. timerdis: this is a timer disable signal which disables the clock input to the timer unit. its function is identical to the disable field of the timerc control register. writ- ing a 0 to the timerdis field will continue the timer op- eration. figure 7 shows a functional view of the effect of the bits of the powerc register on the clock circuitry. it shows only the high-level operation of each bit. not shown are the bits that power down the peripheral units. stop pin assertion (active-low) of the stop pin has the same ef- fect as setting the nock bit in the powerc register. the internal processor clock is synchronously disabled until the stop pin is returned high. once the stop pin is re- turned high, program execution will continue from where it left off without any loss of state. no chip reset is required. the pll remains running, if enabled, during stop assertion. the pllc register bits the pllen bit of the pllc register can be used to power down the clock synthesizer circuitry. before shutting down the clock synthesizer circuitry, the system clock should be switched to either cki using the pllsel bit of pllc, or to the ring oscillator using the slowcki bit of powerc.
data sheet dsp1627 digital signal processor march 2000 30 lucent technologies inc. 4 hardware architecture (continued) notes: the functions in the shaded ovals are bits in the powerc control register. the functions in the nonshaded ovals are bits in the pllc control register. deep sleep is the state arrived at either by a hardware or software stop of the internal processor clock. the switching of the multiplexers and the synchronous gate is designed so that no partial clocks or glitching will occur. when the deep sleep state is entered with the ring oscillator selected, the internal processor clock is turned off before the r ing oscillator is pow- ered down. pll select is the pllsel bit of pllc; pll powerdown is the pllen bit of pllc. figure 7. power management using the powerc and the pllc registers cki2 crystal oscillator, or small signal clock ring oscillator stop xtloff mask-programmable option off cki rstb cmos input clock sync. gate slowcki sync. mux internal processor clock clear nock disable int0 int0en on int1 int1en deep sleep hw stop sw stop nock pllen pllsel pll f vco/2 f slow clock f internal clock f cki deep sleep 5-4124 (f).h
data sheet march 2000 dsp1627 digital signal processor lucent technologies inc. 31 4 hardware architecture (continued) await bit of the alf register setting the await bit of the alf register causes the pro- cessor to go into the standard sleep state or power-sav- ing standby mode. operation of the await bit is the same as in the dsp1610, dsp1611, dsp1616, dsp1617, and dsp1618. in this mode, the minimum circuitry required to process an incoming interrupt re- mains active, and the pll remains active if enabled. an interrupt will return the processor to the previous state, and program execution will continue. the action result- ing from setting the await bit and the action resulting from setting bits in the powerc register are mostly inde- pendent. as long as the processor is receiving a clock, whether slow or fast, the dsp may be put into standard sleep mode with the await bit. once the await bit is set, the stop pin can be used to stop and later restart the processor clock, returning to the standard sleep state. if the processor clock is not running, however, the await bit cannot be set. power management sequencing there are important considerations for sequencing the power management modes. both the crystal oscillator and the small-signal clock input circuits have start-up delays which must be taken into account, and the pll requires a delay to reach lock-in. also, the chip may or may not need to be reset following a return from a low- power state. devices with a crystal oscillator or small-signal input clocking option may use the xtloff bit in the powerc register to power down the on-chip oscillator or small- signal circuitry, thereby reducing the power dissipation. when reenabling the oscillator or the small-signal cir- cuitry, it is important to bear in mind that a start-up inter- val exists during which time the clocks are not stable. two scenarios exist here: 1. immediate turn-off, turn-on with rstb: this sce- nario applies to situations where the target device is not required to execute any code while the crystal os- cillator or small-signal input circuit is powered down and where restart from a reset state can be tolerated. in this case, the processor clock derived from either the oscillator or the small-signal input is running when xtloff is asserted. this effectively stops the inter- nal processor clock. when the system chooses to re- enable the oscillator or small-signal input, a reset of the device will be required. the reset pulse must be of sufficient duration for the oscillator start-up interval to be satisfied. a similar interval is required for the small-signal input circuit to reach its dc operating point. a minimum reset pulse of 20 ms will be ade- quate. the falling edge of the reset signal, rstb, will asynchronously clear the xtloff field, thus re-en- abling the power to the oscillator or small-signal cir- cuitry. the target dsp will then start execution from a reset state, following the rising edge of rstb. 2. running from slow clock while xtloff active: the second scenario applies to situations where the de- vice needs to continue execution of its target code when the crystal oscillator or small-signal input is powered down. in this case, the device switches to the slow ring oscillator clock first, by enabling the slowcki field before writing a 1 to the xtloff field. two nop s are needed in between the two write operations to the powerc register. the target device will then continue execution of its code at slow speed, while the crystal oscillator or small-signal input clock is turned off. switching from the slow clock back to the high-speed crystal oscillator clock is then accom- plished in three user steps. first, xtloff is cleared. then, a user-programmed routine sets the internal timer to a delay to wait for the crystal's oscillations to become stable. when the timer counts down to zero, the high-speed clock is selected by clearing the slowcki field, either in the timer's interrupt service routine or following a timer polling loop. if pll opera- tion is desired, then an additional routine is neces- sary to enable the pll and wait for it to lock.
data sheet dsp1627 digital signal processor march 2000 32 lucent technologies inc. 4 hardware architecture (continued) power management examples without the pll the following examples show the more significant options for reducing the power dissipation. these are valid only if the pllc register is set to disable and deselect the pll (pllen = 0, pllsel = 0). standard sleep mode. this is the standard sleep mode. while the processor is clocked with a high-speed clock, cki, the alf register's await bit is set. peripheral units may be turned off to further reduce the sleep power. powerc = 0x00f0 /* turn off peripherals, core running with cki */ sleep:a0 = 0x8000 /* set alf register in cache loop if running from */ do 1 { /* external memory with >1 wait state */ alf = a0 /* stop internal processor clock, interrupt circuits */ nop /* active */ } nop /* needed for bedtime execution. only sleep power */ nop /* consumed here until.... interrupt wakes up the device */ cont: . . . /* user code executes here */ powerc = 0x0 /* turn peripheral units back on */ sleep with slow internal clock. in this case, the ring oscillator is selected to clock the processor before the device is put to sleep. this will reduce the power dissipation while waiting for an interrupt to continue program execution. powerc = 0x40f0 /* turn off peripherals and select slow clock */ 2*nop /* wait for it to take effect */ sleep:a0 = 0x8000 /* set alf register in cache loop if running from */ do 1 { /* external memory with >1 wait state */ alf = a0 /* stop internal processor clock, interrupt circuits */ nop /* active */ } nop /* needed for bedtime execution. reduced sleep power */ nop /* consumed here.... interrupt wakes up the device */ cont: . . . /* user code executes here */ powerc = 0x00f0 /* select high-speed clock */ 2*nop /* wait for it to take effect */ powerc = 0x0000 /* turn peripheral units back on */ note that, in this case, the wake-up latency is determined by the period of the ring oscillator clock. sleep with slow internal clock and crystal oscillator/small-signal disabled. if the target device contains the crystal oscillator or the small-signal clock option, the clock input circuitry can be powered down to further reduce power. in this case, the slow clock must be selected first. powerc = 0x40f0 /* turn off peripherals and select slow clock */ 2*nop /* wait for it to take effect */ powerc = 0xc0f0 /* turn off the crystal oscillator */ sleep:a0 = 0x8000 /* set alf register in cache loop if running from */ do 1 { /* external memory with >1 wait state */ alf = a0 /* stop internal processor clock, interrupt circuits */ nop /* active */ } nop /* needed for bedtime execution. reduced sleep power */ nop /* consumed here.... interrupt wakes up the device */ powerc = 0x40f0 /* clear xtloff, reenable oscillator/small-signal */ call xtlwait /* wait until oscillator/small-signal is stable */ cont: powerc = 0x00f0 /* select high-speed clock */ 2*nop /* wait for it to take effect */ powerc = 0x0000 /* turn peripheral units back on */ note that, in this case, the wake-up latency is dominated by the crystal oscillator or small-signal start-up period.
data sheet march 2000 dsp1627 digital signal processor lucent technologies inc. 33 4 hardware architecture (continued) software stop. in this case, all internal clocking is disabled. int0, int1, or rstb may be used to reenable the clocks. if the device uses the crystal oscillator or small-signal clock option, the power management must be done in correct sequence. powerc = 0x4000 /* slowcki asserted */ 2*nop /* wait for it to take effect */ powerc = 0xd000 /* xtloff asserted if applicable and int0en asserted */ inc = noint0 /* disable the int0 interrupt */ sopor:powerc = 0xf000 /* nock asserted, all clocks stop */ /* minimum switching power consumed here */ 3*nop /* some nops will be needed */ /* int0 pin clears the nock field, clocking resumes */ cont: powerc = 0x4000 /* int0en cleared and xtloff cleared, if applicable*/ call waitxtl /* wait for the crystal oscillator/small-signal to */ /* stabilize, if applicable*/ powerc = 0x0 /* clear slowcki field, back to high speed */ 2*nop /* wait for it to take effect */ ins = 0x0010 /* clear the int0 status bit */ in this case also, the wake-up latency is dominated by the crystal oscillator or small-signal start-up period. the previous examples do not provide an exhaustive list of options available to the user. many different clocking possibilities exist for which the target device may be programmed, depending on: n the clock source to the processor. n whether the user chooses to power down the peripheral units. n the operational state of the crystal oscillator/small-signal clock input, powered or unpowered. n whether the internal processor clock is disabled through hardware or software. n the combination of power management modes the user chooses. n whether or not the pll is enabled. an example subroutine for xtlwait follows: xtlwait: timer0 = 0x2710 /* load a count of 10,000 into the timer */ timerc = 0x0010 /* start the timer with a prescale of two */ inc = 0x0000 /* disable the interrupts */ loop1: a0 = ins /* poll the ins register */ a0 = a0 & 0x0100 /* check bit 8 (time) of the ins register */ if eq goto loop1 /* loop if the bit is not set */ ins = 0x0100 /* clear the time interrupt bit */ return /* return to the main program */
data sheet dsp1627 digital signal processor march 2000 34 lucent technologies inc. 4 hardware architecture (continued) power management examples with the pll the following examples show the more significant options for reducing power dissipation if operation with the pll clock synthesizer is desired. standard sleep mode, pll running. this mode would be entered in the same manner as without the pll. while the input to the clock synthesizer, cki, remains running, the alf register's await bit is set. the pll will continue to run and dissipate power. peripheral units may be turned off to further reduce the sleep power. powerc = 0x00f0 /* turn off peripherals, core running with pll */ sleep:a0 = 0x8000 /* set alf register in cache loop if running from */ do 1 { /* external memory with >1 wait state */ alf = a0 /* stop internal processor clock, interrupt circuits */ nop /* active */ } nop /* needed for bedtime execution. only sleep power plus pll */ nop /* power consumed here.... interrupt wakes up the device */ cont: . . . /* user code executes here */ powerc = 0x0 /* turn peripheral units back on */ sleep with slow internal clock, pll running . in this case, the ring oscillator is selected to clock the processor before the device is put to sleep. this will reduce power dissipation while waiting for an interrupt to continue program execution. powerc = 0x40f0 /* turn off peripherals and select slow clock */ 2*nop /* wait for slow clock to take effect */ sleep:a0 = 0x8000 /* set alf register in cache loop if running from */ do 1 { /* external memory with >1 wait state */ alf = a0 /* stop internal processor clock, interrupt circuits */ nop /* active */ } nop /* needed for bedtime execution. reduced sleep power, pll */ nop /* power, and ring oscillator power consumed here... */ /* interrupt wakes up the device */ cont: . . . /* user code executes here */ powerc = 0x00f0 /* select high-speed pll based clock */ 2*nop /* wait for it to take effect */ powerc = 0x0000 /* turn peripheral units back on */
data sheet march 2000 dsp1627 digital signal processor lucent technologies inc. 35 4 hardware architecture (continued) sleep with slow internal clock and crystal oscillator/small-signal disabled, pll disabled . if the target de- vice contains the crystal oscillator or the small-signal clock option, the clock input circuitry can be powered down to further reduce power. in this case, the slow clock must be selected first, and then the pll must be disabled, since the pll cannot run without the clock input circuitry being active. powerc = 0x40f0 /* turn off peripherals and select slow clock */ 2*nop /* wait for slow clock to take effect */ pllc = 0x29f2 /* disable pll (assume n = 1,m = 20, lf = 1001) */ powerc = 0xc0f0 /* disable crystal oscillator */ sleep:a0 = 0x8000 /* set alf register in cache loop if running from */ do 1 { /* external memory with >1 wait state */ alf = a0 /* stop internal processor clock, interrupt circuits */ nop /* active */ } nop /* needed for bedtime execution. reduced sleep power nop /* consumed here.... interrupt wakes up device */ powerc = 0x40f0 /* clear xtloff, leave pll disabled */ call xtlwait /* wait until crystal oscillator/small-signal is stable */ pllc = 0xe9f2 /* enable pll, continue to run off slow clock */ call pllwait /* loop to check for lock flag assertion */ cont: powerc = 0x00f0 /* select high-speed pll based clock */ 2*nop /* wait for it to take effect */ powerc = 0x0000 /* turn peripherals back on */ software stop, pll disabled . in this case, all internal clocking is disabled. int0, int1, or rstb may be used to reenable the clocks. if the device uses the crystal oscillator or small-signal clock option, the power management must be done in the correct sequence, with the pll being disabled before shutting down the clock input buffer. powerc = 0x4000 /* slowcki asserted */ 2*nop /* wait for slow clock to take effect */ pllc = 0x29f2 /* disable pll (assume n = 1, m = 20, lf = 1001) */ powerc = 0xd000 /* xtloff asserted, if applicable and int0en /* asserted */ sopor:powerc = 0xf000 /* nock asserted, all clocks stop */ /* minimum switching power consumed here */ 3*nop /* some nops will be needed */ /* int0 pin clears nock field, clocking resumes */ cont: powerc = 0x4000 /* intoen cleared and xtloff cleared, if applicable */ call xtlwait /* wait until crystal oscillator/small-signal is stable */ /* if applicable */ pllc = 0xe9f2 /* enable pll, continue to run off slow clock */ call pllwait /* loop to check for lock flag assertion */ powerc = 0x0 /* select high-speed pll based clock */ 2*nop /* wait for it to take effect */ ins = 0x0010 /* clear the int0 status bit */
data sheet dsp1627 digital signal processor march 2000 36 lucent technologies inc. 5 software architecture 5.1 instruction set the dsp1627 processor has seven types of instruc- tions: multiply/alu, special function, control, f3 alu, bmu, cache, and data move. the multiply/alu instruc- tions are the primary instructions used to implement sig- nal processing algorithms. statements from this group can be combined to generate multiply/accumulate, log- ical, and other alu functions and to transfer data be- tween memory and registers in the data arithmetic unit. the special function instructions can be conditionally executed based on flags from the previous alu or bmu operation, the condition of one of the counters, or the value of a pseudorandom bit in the dsp1627 device. special function instructions perform shift, round, and complement functions. the f3 alu instructions enrich the operations available on accumulators. the bmu in- structions provide high-performance bit manipulation. the control instructions implement the goto and call commands. control instructions can also be executed conditionally. cache instructions are used to implement low-overhead loops, conserve program memory, and decrease the execution time of certain multiply/alu in- structions. data move instructions are used to transfer data between memory and registers or between accu- mulators and registers. see the dsp1611/17/18/27 digital signal processor information manual for a de- tailed description of the instruction set. the following operators are used in describing the in- struction set: n * 16 x 16-bit C> 32-bit multiplication or register-in- direct addressing when used as a prefix to an ad- dress register or denotes direct addressing when used as a prefix to an immediate n + 36-bit addition ? n C 36-bit subtraction ? n >> arithmetic right shift n >>> logical right shift n << arithmetic left shift n <<< logical left shift n | 36-bit bitwise or ? n & 36-bit bitwise and ? n ^ 36-bit bitwise exclusive or ? n : compound address swapping, accumulator shuffling n ~ one's complement ? these are 36-bit operations. one operand is 36-bit data in an ac- cumulator; the other operand may be 16, 32, or 36 bits. multiply/alu instructions note that the function statements and transfer state- ments in table 13 are chosen independently. any func- tion statement (f1) can be combined with any transfer statement to form a valid multiply/alu instruction. if ei- ther statement is not required, a single statement from either column also constitutes a valid instruction. the number of cycles to execute the instruction is a function of the transfer column. (an instruction with no transfer statement executes in one instruction cycle.) whenever pc, pt, or rm is used in the instruction and points to ex- ternal memory, the programmed number of wait-states must be added to the instruction cycle count. all multi- ply/alu instructions require one word of program mem- ory. the no-operation ( nop ) instruction is a special- case encoding of a multiply/alu instruction and exe- cutes in one cycle. the assembly-language representa- tion of a nop is either nop or a single semicolon. a single-cycle squaring function is provided in dsp1627. by setting the x = y = bit in the auc register, any instruction that loads the high half of the y register also loads the x register with the same value. a subse- quent instruction to multiply the x register and y register results in the square of the value being placed in the p register. the instruction a0 = p p = x*y y = *r0++ with the x = y = bit set to one will read the value pointed to by r0, load it to both x and y, multiply the previously fetched value of x and y, and transfer the previous prod- uct to a0. a table of values pointed to by r0 can thus be squared in a pipeline with one instruction cycle per each value. multiply/alu instructions that use x = x transfer statements (such as a0 = p p = x*y y = *r0++ x = *pt++) are not recommended for squaring because pt will be incremented even though x is not loaded from the value pointed to by pt. also, the same conflict wait occurrenc- es from reading the same bank of internal memory or reading from external memory apply, since the x space fetch occurs (even though its value is not used).
data sheet march 2000 dsp1627 digital signal processor lucent technologies inc. 37 5 software architecture (continued) ? the l in [ ] is an optional argument that specifies the low 16 bits of at or y. ? add cycles for: 1. when an external memory access is made in x or y space and wait-states are programmed, add the number of wait-states. 2. if an x space access and a y space access are made to the same bank of dpram in one instruction, add one cycle. note: for transfer statements when loading the upper half of an accumulator, the lower half is cleared if the corre- sponding clr bit in the auc register is zero. auc is cleared by reset. table 13. multiply/alu instructions function statement transfer statement ? cycles (out/in cache) ? p = x * y y = y x = x 2/1 ad = p p = x * y y = at x = x 2/1 ad = as + p p = x * y y[l] = y 1/1 ad = as C p p = x * y at[l] = y 1/1 ad = p x = y 1/1 ad = as + p y 1/1 ad = as C p y = y[l] 2/2 ad = y y = at[l] 2/2 ad = as + y z:y x = x 2/2 ad = as C y z:y[l] 2/2 ad = as & y z:at[l] 2/2 ad = as | y ad = as ^ y as C y as & y table 14. replacement table for multiply/alu instructions replace value meaning ad, as, at a0, a1 one of two dau accumulators. x *pt++, *pt++i x memory space location pointed to by pt. pt is postmodified by +1 and i, respectively. y *rm, *rm++, *rm--, rm++j ram location pointed to by rm (m = 0, 1, 2, 3). rm is postmodified by 0, +1, C1, or j, respectively. z *rmzp, *rmpz, *rmm2, *rmjk read/write compound addressing. rm (m = 0, 1, 2, 3) is used twice. first, postmodified by 0, +1, C1, or j, respectively; and, second, post- modified by +1, 0, +2, or k, respectively.
data sheet dsp1627 digital signal processor march 2000 38 lucent technologies inc. 5 software architecture (continued) special function instructions all forms of the special function require one word of program memory and execute in one instruction cycle. (if pc points to external memory, add programmed wait-states.) ad = as load destination accumulator from source accumulator ad = Cas 2's complement ad = ~as * 1's complement ad = rnd(as) round upper 20 bits of accumulator adh = ash + 1 increment upper half of accumulator (lower half cleared) ad = as + 1 increment accumulator ad = y load accumulator with 32-bit y register value with sign extend ad = p load accumulator with 32-bit p register value with sign extend the above special functions can be conditionally executed, as in: if con instruction and with an event counter ifc con instruction which means: if con is true then c1 = c1 + 1 instruction c2 = c1 else c1 = c1 + 1 the above special function statements can be executed unconditionally by writing them directly, e.g., a0 = a1. ad = as >> 1 ad = as >> 4 ad = as >> 8 ad = as >> 16 } arithmetic right shift (sign preserved) of 36-bit accumulators * this function is not available for the dsp16a. ad = as << 1 ad = as << 4 ad = as << 8 ad = as << 16 } arithmetic left shift (sign not preserved) of the lower 32 bits of accumulators (upper 4 bits are sign-bit-extended from bit 31 at the completion of the shift) table 15. replacement table for special function instructions replace value meaning ad as a0, a1 one of two dau accumulators. con mi, pl, eq, ne, gt, le, lvs, lvc, mvs, mvc, c0ge, c0lt, c1ge, c1lt, heads, tails, true, false, allt, allf, somet, somef, oddp, evenp, mns1, nmns1, npint, njint, lock see table 17 for definitions of mnemonics.
data sheet march 2000 dsp1627 digital signal processor lucent technologies inc. 39 5 software architecture (continued) control instructions all control instructions executed unconditionally execute in two cycles, except icall which takes three cycles. control instructions executed conditionally execute in three instruction cycles. (if pc, pt, or pr point to external memory, add programmed wait-states.) control instructions executed unconditionally require one word of program memory, while control instructions executed conditionally require two words. control instructions cannot be executed from the cache. goto ja ? goto pt call ja ? call pt icall ? return (goto pr) ireturn (goto pi) ?the goto ja and call ja instructions should not be placed in the last or next-to-last instruction before the boundary of a 4 kwords page. if the goto or call is placed there, the program counter will have incremented to the next page and the jump will be to the next page, rather than to the desired current page. ?the icall instruction is reserved for development system use. the above control instructions, with the exception of ireturn and icall , can be conditionally executed. for example: if le goto 0x0345 table 16. replacement table for control instructions replace value meaning con mi, pl, eq, ne, gt, le, nlvs, lvc, mvs, mvc, c0ge, c0lt, c1ge, c1lt, heads, tails, true, false, allt, allf, somet, somef, oddp, evenp, mns1, nmns1, npint, njint, lock see table 17 for definitions of mnemonics. ja 12-bit value least significant 12 bits of absolute address within the same 4 kwords memory section.
data sheet dsp1627 digital signal processor march 2000 40 lucent technologies inc. 5 software architecture (continued) conditional mnemonics (flags) table 17 lists mnemonics used in conditional execution of special function and control instructions. notes: testing the state of the counters (c0 or c1) automatically increments the counter by one. the heads or tails condition is determined by a randomly set or cleared bit, respectively. the bit is randomly set with a proba bility of 0.5. a random rounding function can be implemented with either heads or tails. the random bit is generated by a ten-stage pseudorandom sequen ce generator (psg) that is updated after either a heads or tails test. the pseudorandom sequence may be reset by writing any value to the pi register, except during an interrupt service routine (isr). while in an isr, writing to the pi register updates the register and does not reset the psg. if not in an isr, writing to the pi register resets the psg. (the pi register is updated, but will be written with the contents of the pc on the next instruction.) interrupts must be disabled when writing to the pi register. if an interrupt is taken after the pi write, but before pi is updated with the pc value, the ireturn instruction will not return to the correct location. if the rand bit in the auc register is set, however, writing the pi regis ter never resets the psg. table 17. dsp1627 conditional mnemonics test meaning test meaning pl result is nonnegative (sign bit is bit 35). 3 0 mi result is negative. < 0 eq result is equal to 0. = 0 ne result is not equal to 0. 1 0 gt result is greater than 0. > 0 le result is less than or equal to 0. 0 lvs logical overflow set. * * result is not representable in the 36-bit accumulators (36-bit overflow). lvc logical overflow clear. mvs mathematical overflow set. ? ? bits 3531 are not the same (32-bit overflow). mvc mathematical overflow clear. c0ge counter 0 greater than or equal to 0. c0lt counter 0 less than 0. c1ge counter 1 greater than or equal to 0. c1lt counter 1 less than 0. heads pseudorandom sequence bit set. tails pseudorandom sequence bit clear. true the condition is always satisfied in an if in- struction. false the condition is never satisfied in an if instruc- tion. allt all true, all bio input bits tested compared successfully. allf all false, no bio input bits tested compared successfully. somet some true, some bio input bits tested com- pared successfully. somef some false, some bio input bits tested did not compare successfully. oddp odd parity, from bmu operation. evenp even parity, from bmu operation. mns1 minus 1, result of bmu operation. nmns1 not minus 1, result of bmu operation. npint not pint, used by hardware development system. njint not jint, used by hardware development system. lock the pll has achieved lock and is stable.
data sheet march 2000 dsp1627 digital signal processor lucent technologies inc. 41 5 software architecture (continued) f3 alu instructions these instructions are implemented in the dsp1600 core. they allow accumulator two-operand operations with ei- ther another accumulator, the p register, or a 16-bit immediate operand (im16). the result is placed in a destination accumulator that can be independently specified. all operations are done with the full 36 bits. for the accumulator with accumulator operations, both inputs are 36 bits. for the accumulator with p register operations, the p register is sign-extended into bits 3532 before the operation. for the accumulator high with immediate operations, the im- mediate is sign-extended into bits 3532 and the lower bits 150 are filled with zeros, except for the and opera- tion, for which they are filled with ones. these conventions allow the user to do operations with 32-bit immediates by programming two consecutive 16-bit immediate operations. the f3 alu instructions are shown in table 18. note: the f3 alu instructions that do not have a destination accumulator are used to set flags for conditional operations, i.e., bit test operations. ? if pc points to external memory, add programmed wait-states. ? the h and l are required notation in these instructions. f4 bmu instructions the bit manipulation unit in the dsp1627 provides a set of efficient bit manipulation operations on accumulators. it contains four auxiliary registers, ar<03> (arm, m = 0, 1, 2, 3), two alternate accumulators (aa0aa1), which can be shuffled with the working set, and four flags (oddp, evenp, mns1, and nmns1). the flags are testable by condi- tional instructions and can be read and written via bits 47 of the alf register. the bmu also sets the lmi, leq, llv, and lmv flags in the psw register. n lmi = 1 if negative (i.e., bit 35 = 1) n leq = 1 if zero (i.e., bits 350 are 0) n llv = 1 if (a) 36-bit overflow, or if (b) illegal shift on field width/offset condition n lmv = 1 if bits 3135 are not the same (32-bit overflow) the bmu instructions and cycle times follow. (if pc points to external memory, add programmed wait-states.) all bmu instructions require 1 word of program memory unless otherwise noted. please refer to the dsp1611/17/18/ 27 digital signal processor information manual for further discussion of the bmu instructions. table 18. f3 alu instructions f3 alu instructions ? cachable (one-cycle) not cachable (two-cycle) ? ad = as + at ad = as C at ad = as & at ad = as | at ad =as ^ at as C at as & at ad = as + p ad = as C p ad = as & p ad = as | p ad = as ^ p as C p as & p ad = ash + im16 ad = ash C im16 ad = ash & im16 ad = ash | im16 ad = ash ^ im16 ash C im16 ash & im16 ad = asl + im16 ad = asl C im16 ad = asl & im16 ad = asl | im16 ad = asl ^ im16 asl C im16 asl & im16
data sheet dsp1627 digital signal processor march 2000 42 lucent technologies inc. 5 software architecture (continued) n barrel shifter: ad = as >> im16 arithmetic right shift by immediate (36-bit, sign filled in); 2-cycle, 2-word. ad = as >> arm arithmetic right shift by arm (36-bit, sign filled in); 1-cycle. ad = as >> as arithmetic right shift by as (36-bit, sign filled in); 2-cycle. ad = as >>> im16 logical right shift by immediate (32-bit shift, 0s filled in); 2-cycle, 2-word. ad = as >>> arm logical right shift by arm (32-bit shift, 0s filled in); 1-cycle. ad = as >>> as logical right shift by as (32-bit shift, 0s filled in); 2-cycle. ad = as << im16 arithmetic left shift ? by immediate (36-bit shift, 0s filled in); 2-cycle, 2-word. ad = as << arm arithmetic left shift ? by arm (36-bit shift, 0s filled in); 1-cycle. ad = as << as arithmetic left shift ? by as (36-bit shift, 0s filled in); 2-cycle. ad = as <<< im16 logical left shift by immediate (36-bit shift, 0s filled in); 2-cycle, 2-word. ad = as <<< arm logical left shift by arm (36-bit shift, 0s filled in); 1-cycle. ad = as <<< as logical left shift by as (36-bit shift, 0s filled in); 2-cycle. ? not the same as the special function arithmetic left shift. here, the guard bits in the destination accumulator are shifted in to, not sign-extended. n normalization and exponent computation: ad = exp(as) detect the number of redundant sign bits in accumulator; 1-cycle. ad = norm(as, arm) normalize as with respect to bit 31, with exponent in arm; 1-cycle. n bit field extraction and insertion: ad = extracts(as, im16) extraction with sign extension, field specified as immediate; 2-cycle, 2-word. ad = extracts(as, arm) extraction with sign extension, field specified in arm; 1-cycle. ad = extractz(as, im16) extraction with zero extension, field specified as immediate; 2-cycle, 2-word. ad = extractz(as, arm) extraction with zero extension, field specified in arm; 1-cycle. ad = insert(as, im16) bit field insertion, field specified as immediate; 2-cycle, 2-word. ad = insert(as, arm) bit field insertion, field specified in arm; 2-cycle. note: the bit field to be inserted or extracted is specified as follows. the width (in bits) of the field is the upper byte of the operand (immediate or arm), and the offset from the lsb is in the lower byte. n alternate accumulator set: ad = as:aa0 shuffle accumulators with alternate accumulator 0 (aa0); 1-cycle. ad = as:aa1 shuffle accumulators with alternate accumulator 1 (aa1); 1-cycle. note: the alternate accumulator gets what was in as. ad gets what was in the alternate accumulator. table 19. replacement table for f3 alu instructions and f4 bmu instructions replace value meaning ad, at, as a0 or a1 one of the two accumulators. im16 immediate 16-bit data, sign-, zero-, or one-extended as appropriate. arm ar<03> one of the auxiliary bmu registers.
data sheet march 2000 dsp1627 digital signal processor lucent technologies inc. 43 5 software architecture (continued) cache instructions cache instructions require one word of program memory. the do instruction executes in one instruction cycle, and the redo instruction executes in two instruction cycles. (if pc points to external memory, add programmed wait- states.) control instructions and long immediate values cannot be stored inside the cache. the instruction formats are as follows: n do k { n instr1 n instr2 n . n . n . n instrn n } n redo k ? the assembly-language statement, do cloop (or redo cloop ), is used to specify that the number of iterations is to be taken from the cloop register. k is encoded as 0 in the instruction encoding to select cloop . when the cache is used to execute a block of instructions, the cycle timings of the instructions are as follows: 1. in the first pass, the instructions are fetched from program memory and the cycle times are the normal out-of- cache values, except for the last instruction in the block of ni instructions. this instruction executes in two cycles. 2. during pass two through pass k C 1, each instruction is fetched from cache and the in-cache timings apply. 3. during the last (kth) pass, the block of instructions is fetched from cache and the in-cache timings apply, except that the timing of the last instruction is the same as if it were out-of-cache. 4. if any of the instructions access external memory, programmed wait-states must be added to the cycle counts. the redo instruction treats the instructions currently in the cache memory as another loop to be executed k times. using the redo instruction, instructions are reexecuted from the cache without reloading the cache. the number of iterations, k, for a do or redo can be set at run time by first moving the number of iterations into the cloop register (7 bits unsigned), and then issuing the do cloop or redo cloop . at the completion of the loop, the value of cloop is decremented to 0; hence, cloop needs to be written before each do cloop or redo cloop . table 20. replacement table for cache instructions replace instruction encoding meaning k cloop ? number of times the instructions are to be executed taken from bits 06 of the cloop register. 1 to 127 number of times the instructions to be executed is encoded in the instruction. n 1 to 15 1 to 15 instructions can be included.
data sheet dsp1627 digital signal processor march 2000 44 lucent technologies inc. 5 software architecture (continued) data move instructions data move instructions normally execute in two instruction cycles. (if pc or rm point to external memory, any pro- grammed wait-states must be added. in addition, if pc and rm point to the same bank of dpram, then one cycle must be added.) immediate data move instructions require two words of program memory; all other data move in- structions require only one word. the only exception to these statements is a special case immediate load (short immediate) instruction. if a yaau register is loaded with a 9-bit short immediate value, the instruction requires only one word of memory and executes in one instruction cycle. all data move instructions, except those doing long im- mediate loads, can be executed from within the cache. the data move instructions are as follows: n r = im16 n at[l] = r n sr = im9 n y = r n r = y n z : r n r = as[l] n dr = * (offset) n * (offset) = dr notes: sioc, sioc2, tdms, tdms2, srta, and srta2 registers are not readable. when signed registers less than 16 bits wide (c0, c1, c2) are read, their contents are sign-extended to 16 bits. when unsigned registers less than 16 bits wide are read, their contents are zero-extended to 16 bits. loading an accumulator with a data move instruction does not affect the flags. table 21. replacement table for data move instructions replace value meaning r any of the registers in table 51 dr r<03>, a0[l], a1[l], y[l], p, pl, x, pt, pr, psw subset of registers accessible with direct addressing. as, at a0, a1 high half of accumulator. y * rm, * rm++, * rm--, * rm++j same as in multiply/alu instructions. z * rmzp, * rmpz, * rmm2, * rmjk same as in multiply/alu instructions. im16 16-bit value long immediate data. im9 9-bit value short immediate data for yaau registers. offset 5-bit value from instruction 11-bit value in base register value in bits [15:5] of ybase register form the 11 most significant bits of the base address. the 5-bit offset is concatenated to this to form a 16-bit address. sr r<03>, rb, re, j, k subset of registers for short immediate.
data sheet march 2000 dsp1627 digital signal processor lucent technologies inc. 45 5 software architecture (continued) 5.2 register settings tables 22 through 38 describe the programmable registers of the dsp1627 device. table 40 describes the register settings after reset. note that the following abbreviations are used in the tables: n x = don't care n r = read only n w = read/write the reserved (rsvd) bits in the tables should always be written with zeros to make the program compatible with future chip versions. table 22. serial i/o control registers * see tdms register, sync field. ? see tdms register, sync field. ? the bit definitions of the sioc2 register are identical to the sioc register bit definitions. sioc bit 10987654321 0 field dodly ld clk msb old ild ock ick olen ilen field value description dodly 0 1 do changes on the rising edge of ock. do changes on the falling edge of ock. this delay in driving do increases the hold time on do by half a cycle of ock. ld 0 1 in active mode, ild1 and/or old1 = ick1/16, active sync1 = ick1/[128/256*]. in active mode, ild1 and/or old1 = ock1/16, active sync1 = ock1/[128/256*]. clk 00 01 10 11 active clock = cki/2 (1x). active clock = cki/6 (1x). active clock = cki/8 (1x). active clock = cki/10 (1x). msb 0 1 lsb first. msb first. old 0 1 old1 is an input (passive mode). old1 is an output (active mode). ild 0 1 ild1 is an input (passive mode). ild1 is an output (active mode). ock 0 1 ock1 is an input (passive mode). ock1 is an output (active mode). ick 0 1 ick1 is an input (passive mode). ick1 is an output (active mode). olen 0 1 16-bit output. 8-bit output. ilen 0 1 16-bit input. 8-bit input. sioc2 ? bit 109876543210 field dodly2 ld2 clk2 msb2 old2 ild2 ock2 ick2 olen2 ilen2
data sheet dsp1627 digital signal processor march 2000 46 lucent technologies inc. 5 software architecture (continued) table 23. time-division multiplex slot registers ? see sioc register, ld field. ? select this mode when in multiprocessor mode. the tdms2 register bit definitions are identical to the tdms register bit definitions. tdms bit 9 8 7654321 0 field syncsp mode transmit slot sync field value description syncsp ? 0 ? 1 sync1 = ick1/128 if ld = 0 * . sync1 = ock1/128 if ld = 1*. sync1 = ick1/256 if ld = 0*. sync1 = ock1/256 if ld = 1*. * see sioc register, ld field. ? select this mode when in multiprocessor mode. mode 0 multiprocessor mode off; doen1 is an input (passive mode). 1 multiprocessor mode on; doen1 is an output (active mode). transmit slot 1xxxxxx transmit slot 7. x1xxxxx transmit slot 6. xx1xxxx transmit slot 5. xxx1xxx transmit slot 4. xxxx1xx transmit slot 3. xxxxx1x transmit slot 2. xxxxxx1 transmit slot 1. sync 1 transmit slot 0, sync1 is an output (active mode). 0 sync1 is an input (passive mode). tdms2 bit 9 8 7654321 0 field syncsp2 ? mode2 transmit slot2 sync2
data sheet march 2000 dsp1627 digital signal processor lucent technologies inc. 47 5 software architecture (continued) table 24. serial receive/transmit address registers ? the srta2 field definitions are identical to the srta register field definitions. table 25. multiprocessor protocol registers ? the saddx2 field definitions are identical to the saddx register field definitions. srta bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field receive address transmit address field value description receive address 1xxxxxxx receive address 7. x1xxxxxx receive address 6. xx1xxxxx receive address 5. xxx1xxxx receive address 4. xxxx1xxx receive address 3. xxxxx1xx receive address 2. xxxxxx1x receive address 1. xxxxxxx1 receive address 0. transmit address 1xxxxxxx transmit address 7. x1xxxxxx transmit address 6. xx1xxxxx transmit address 5. xxx1xxxx transmit address 4. xxxx1xxx transmit address 3. xxxxx1xx transmit address 2. xxxxxx1x transmit address 1. xxxxxxx1 transmit address 0. srta2 ? bit 1514131211109876543210 field receive address2 transmit address2 saddx bit field 158 70 write x write protocol field [7:0] read read protocol field [7:0] 0 saddx2 ? bit field 158 70 write x write protocol2 field [7:0] read read protocol2 field [7:0] 0
data sheet dsp1627 digital signal processor march 2000 48 lucent technologies inc. 5 software architecture (continued) ? the auc is 9 bits [8:0]. the upper 7 bits [15:9] are always zero when read and should always be written with zeros to make the program compatible with future chip versions. the auc register is cleared at reset. table 26. processor status word (psw) register bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field dau flags x x a1[v] a1[35:32] a0[v] a0[35:32] field value description dau flags * * the dau flags can be set by either bmu or dau operations. wxxx lmi logical minus when set (bit 35 = 1). xwxx leq logical equal when set (bit [35:0] = 0). xxwx llv logical overflow when set. xxxw lmv mathematical overflow when set. a1[v] w accumulator 1 (a1) overflow when set. a1[35:32] wxxx accumulator 1 (a1) bit 35. xwxx accumulator 1 (a1) bit 34. xxwx accumulator 1 (a1) bit 33. xxxw accumulator 1 (a1) bit 32. a0[v] w accumulator 0 (a0) overflow when set. a0[35:32] wxxx accumulator 0 (a0) bit 35. xwxx accumulator 0 (a0) bit 34. xxwx accumulator 0 (a0) bit 33. xxxw accumulator 0 (a0) bit 32. table 27. arithmetic unit control (auc) register ? bit 8 7654321 0 field rand x=y= clr sat align field value description rand 0 1 pseudorandom sequence generator (psg) reset by writing the pi register only outside an interrupt service routine. psg never reset by writing the pi register. x=y= 0 1 normal operation. all instructions which load the high half of the y register also load the x regis- ter, allowing single-cycle squaring with p = x * y. clr 1xx clearing yl is disabled (enabled when 0). x1x clearing a1l is disabled (enabled when 0). xx1 clearing a0l is disabled (enabled when 0). sat 1x a1 saturation on overflow is disabled (enabled when 0). x1 a0 saturation on overflow is disabled (enabled when 0). align 00 a0, a1 ? p. 01 a0, a1 ? p/4. 10 a0, a1 ? p x 4 (and zeros written to the two lsbs). 11 a0, a1 ? p x 2 (and zero written to the lsb).
data sheet march 2000 dsp1627 digital signal processor lucent technologies inc. 49 5 software architecture (continued) encoding: a 0 disables an interrupt; a 1 enables an interrupt. encoding: a 0 indicates no interrupt. a 1 indicates an interrupt has been recognized and is pending or being serviced. if a 1 is written to bits 4, 5, or 8 of ins, the corresponding interrupt is cleared. table 28. parallel host interface control (phifc) register bit 157 6 5 4 3 2 1 0 field rsvd psobef pflagsel pflag pbself pstrb pstrobe pmode field value description pmode 0 1 8-bit data transfers. 16-bit data transfers. pstrobe 0 1 intel protocol: pids and pods data strobes. motorola protocol: prwn and pds data strobes. pstrb 0 1 when pstrobe = 1, pods pin (pds) active-low. when pstrobe = 1, pods pin (pds) active-high. pbself 0 1 in either mode, pbsel pin = 0 ? pdx0 low byte. see table 7. if pmode = 0, pbsel pin = 1 ? pdx0 low byte. if pmode = 1, pbsel pin = 0 ? pdx0 high byte. pflag 0 1 pibf and pobe pins active-high. pibf and pobe pins active-low. pflagsel 0 1 normal. pibf flag ored with pobe flag and output on pibf pin; pobe pin un- changed (output buffer empty). psobef 0 1 normal. pobe flag as read through pstat register is active-low. table 29. interrupt control (inc) register bit 15 1411 10 9 8 76 54 3 2 1 0 field jint * * jint is a jtag interrupt and is controlled by the hds. it may be made unmaskable by the lucent technologies development system tools. rsvd obe2 ibf2 time rsvd int[1:0] pibf pobe obe ibf table 30. interrupt status (ins) register bit 15 1411 10 9 8 76 54 3 2 1 0 field jint rsvd obe2 ibf2 time rsvd int[1:0] pibf pobe obe ibf
data sheet dsp1627 digital signal processor march 2000 50 lucent technologies inc. 5 software architecture (continued) table 31. timerc register bit 157 6 5 4 30 field rsvd disable reload t0en prescale field value description disable 0 1 timer enabled. timer and prescaler disabled. the period register and timer0 are not reset. reload 0 1 timer stops after counting down to 0. timer automatically reloads and repeats indefinitely. t0en 0 1 timer holds current count. timer counts down to 0. prescale see table below. prescale field prescale frequency of timer interrupts prescale frequency of timer interrupts 0000 cko/2 1000 cko/512 0001 cko/4 1001 cko/1024 0010 cko/8 1010 cko/2048 0011 cko/16 1011 cko/4096 0100 cko/32 1100 cko/8192 0101 cko/64 1101 cko/16384 0110 cko/128 1110 cko/32768 0111 cko/256 1111 cko/65536 table 32. phase-locked loop control (pllc) register bit 15 14 13 12 118 75 40 field pllen pllsel icp sel5v lf[3:0] nbits[2:0] mbits[4:0] field value description pllen 0 1 pll powered down. pll powered up. pllsel 0 1 dsp internal clock taken directly from cki. dsp internal clock taken from pll. icp charge pump current selection (see table 64 for proper value). sel5v 0 1 3 v operation (see table 64 for proper value). 5 v operation (see table 64 for proper value). lf[3:0] loop filter setting (see table 64 for proper value). nbits[2:0] encodes n, 1 n 8, where n = nbits[2:0] + 2, unless nbits[2:0] = 111, then n = 1. mbits[4:0] encodes m, 2 m 20, where m = mbits[4:0] + 2, f internal clock = f cki x (m/(2n)).
data sheet march 2000 dsp1627 digital signal processor lucent technologies inc. 51 5 software architecture (continued) table 33. sbit register bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field direc[7:0] value[7:0] field value description direc 1xxxxxxx iobit7 is an output (input when 0). x1xxxxxx iobit6 is an output (input when 0). xx1xxxxx iobit5 is an output (input when 0). xxx1xxxx iobit4 is an output (input when 0). xxxx1xxx iobit3 is an output (input when 0). xxxxx1xx iobit2 is an output (input when 0). xxxxxx1x iobit1 is an output (input when 0). xxxxxxx1 iobit0 is an output (input when 0). value rxxxxxxx reads the current value of iobit7. xrxxxxxx reads the current value of iobit6. xxrxxxxx reads the current value of iobit5. xxxrxxxx reads the current value of iobit4. xxxxrxxx reads the current value of iobit3. xxxxxrxx reads the current value of iobit2. xxxxxxrx reads the current value of iobit1. xxxxxxxr reads the current value of iobit0. table 34. cbit register bit 1514131211109876543210 field mode/mask[7:4] mode/mask[3:0] data/pat[7:4] data/pat[3:0] direc[n] * *0 n 7. mode/mask[n] data/pat[n] action 1 (output) 0 0 clear 1 (output) 0 1 set 1 (output) 1 0 no change 1 (output) 1 1 toggle 0 (input) 0 0 no test 0 (input) 0 1 no test 0 (input) 1 0 test for zero 0 (input) 1 1 test for one
data sheet dsp1627 digital signal processor march 2000 52 lucent technologies inc. 5 software architecture (continued) if the exm pin is high and the int1 is low upon reset, the mwait register is initialized to all 1s (15 wait-states for all external memory). otherwise, the mwait register is initialized to all 0s (0 wait-states) upon reset. table 35. alf register bit 15 14 130 field await lowpr flags field value action await 1 0 power-saving standby mode or standard sleep enabled. normal operation. lowpr 1 0 the internal dpram is addressed beginning at 0x0000 in x space. the internal dpram is addressed beginning at 0xc000 in x space. flags see table below. bit flag use 138 reserved 7 nmns1 not-minus-one from bmu 6 mns1 minus-one from bmu 5 evenp even parity from bmu 4 oddp odd parity from bmu 3 somef some false from bio 2 somet some true from bio 1 allf all false from bio 0 allt all true from bio table 36. mwait register bit 1512 118 74 30 field erom[3:0] eramhi[3:0] io[3:0] eramlo[3:0] table 37. dsp1627 32-bit jtag id register bit 31 30 2928 2719 1812 110 field reserved secure clock romcode part id 0x03b field value mask-programmable features reserved 0 secure 0 1 nonsecure rom option. secure rom option. clock 01 10 11 small-signal input clock option. crystal oscillator input clock option. cmos level input clock option. romcode users romcode id: the romcode id is the 9-bit binary value of the following expression: (20 x value for first letter) + (value of second letter), where the values of the letters are in the following table. for example, romcode gk is (20 x 6) + (9) = 129 or 0 1000 0001. part id 0x1c dsp1627x36 with 36k irom and no erom in map1 or map3. 0x2c dsp1627x32 with 32k irom and 16k erom in map1 and map3. romcode letter abcdefghjklmnprstuwy value 012345678910111213141516171819
data sheet march 2000 dsp1627 digital signal processor lucent technologies inc. 53 5 software architecture (continued) table 38. ioc register * * the field definitions for the ioc register are different from the dsp1610. bit 15 14 13 12 11 10 9 87 64 30 field rsvd extrom cko2 ebioh werom esio2 siolbc cko[1:0] rsvd denb[3:0] ioc fields ioc field description extrom if 1, sets ab15 low during external memory accesses when werom = 1. cko2 cko configuration (see below). ebioh if 1, enables high half of bio, iobit[4:7], and disables vec[3:0] from pins. werom if 1, allows writing into external program (x) memory. esio2 if 1, enables sio2 and low half of bio, and disables phif from pins. siolbc if 1, do1 and do2 looped back to di1 and di2. cko[1:0] cko configuration (see below). denb3 if 1, delay erom. denb2 if 1, delay eramhi. denb1 if 1, delay io. denb0 if 1, delay eramlo. cko2 cko1 cko0 cko output description 1x pll 0 0 0 cki cki x m/(2n) free-running clock. 0 0 1 cki/(1 + w) cki x (m/(2n)) / [1 + w] wait-stated clock. * , ? * the phase of cki is synchronized by the rising edge of rstb. ? when slowcki is enabled in the powerc register, these options reflect the low-speed internal ring oscillator. 010 1 1 held high.*, ? , ? ? the wait-stated clock reflects the internal instruction cycle and may be stretched based on the mwait register setting (see ta ble 36). during sequenced external memory accesses, it completes one cycle. the sequenced wait-stated clock completes two cycles during a sequenced external memory access and may be stretched based on t he mwait register setting (see table 36). 0 1 1 0 0 held low. 1 0 0 cki cki output of cki buffer. 1 0 1 cki/(1 + w) cki x (m/(2n)) / [1 + w] sequenced, wait-stated clock.*, ? , ? , 1 1 0 reserved 1 1 1 reserved
data sheet dsp1627 digital signal processor march 2000 54 lucent technologies inc. 5 software architecture (continued) table 39. powerc register note: the reserved (rsvd) bits should always be written with zeros to make the program compatible with future chip versions. a ? indicates that this bit is unknown on powerup reset and unaffected on subsequent reset. an s indicates that this bit shadows the pc. p indicates the value on an input pin, i.e., the bit in the register reflects the value on the corre- sponding input pin. ? if exm is high and int1 is low when rstb goes high, mwait will contain all ones instead of all zeros. the powerc register configures various power management modes. bit 15 14 13 12 11 10 98 7 6 5 4 30 field xtloff slowcki nock int0en rsvd int1en rsvd sio1dis sio2dis phifdis timerdis rsvd powerc fields field description xtloff 1 = powerdown crystal oscillator or small-signal clock input. slowcki 1 = select ring oscillator clock (internal slow clock). nock 1 = disable internal processor clock. int0en 1 = int0 clears nock field. int1en 1 = int1 clears nock field. sio1dis 1 = disable sio1. sio2dis 1 = disable sio2. phifdis 1 = disable phif. timerdis 1 = disable timer. table 40. register settings after reset register bits 150 register bits 150 r0 ???????????????? inc 0000000000000000 r1 ???????????????? ins 0000010000000110 r2 ???????????????? sdx2 ???????????????? r3 ???????????????? saddx ???????????????? j ???????????????? cloop 000000000??????? k ???????????????? mwait 0000000000000000 ? rb 0000000000000000 saddx2 ???????????????? re 0000000000000000 sioc2 ??????0000000000 pt ???????????????? cbit ???????????????? pr ???????????????? sbit 00000000pppppppp pi ssssssssssssssss ioc 0000000000000000 i ???????????????? jtag ???????????????? p ???????????????? pl ???????????????? a0 ???????????????? x ???????????????? a0l ???????????????? y ???????????????? a1 ???????????????? yl ???????????????? a1l ???????????????? auc 0000000000000000 timerc ????????00000000 psw ????00?????????? timer0 0000000000000000 c0 ???????????????? tdms2 ??????0000000000 c1 ??????????????? srta2 ???????????????? c2 ???????????????? powerc 0000000000000000 sioc ??????0000000000 pllc 0000000000000000 srta ???????????????? ar0 ???????????????? sdx ???????????????? ar1 ???????????????? tdms ??????0000000000 ar2 ???????????????? phifc 0000000000000000 ar3 ???????????????? pdx0 0000000000000000 ybase ???????????????? alf 00000000????????
data sheet march 2000 dsp1627 digital signal processor lucent technologies inc. 55 5 software architecture (continued) 5.3 instruction set formats this section defines the hardware-level encoding of the dsp1627 device instructions. multiply/alu instructions special function instructions format 1: multiply/alu read/write group field tdsf1xy bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 format 1a: multiply/alu read/write group field tatsf1xy bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 format 2: multiply/alu read/write group field tdsf1xy bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 format 2a: multiply/alu read/write group field tatsf1xy bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 format 3: f2 alu special functions field tdsf2 con bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 format 3a: f3 alu operations field t d s f3 src2 at 0 1 immediate operand (im16) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 format 3b: bmu operations field t d s f4[31] 0 f4[0] ar immediate operand (im16) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
data sheet dsp1627 digital signal processor march 2000 56 lucent technologies inc. 5 software architecture (continued) control instructions note: a branch instruction immediately follows except for a software interrupt (icall). data move instructions cache instructions format 4: branch direct group field tja bit 1514131211109876543210 format 5: branch indirect group field tb reserved0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 format 6: conditional branch qualifier/software interrupt (icall) field t si reserved con bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 format 7: data move group field tat r y/z bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 format 8: data move (immediate operand2 words) field t d r reserved immediate operand (im16) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 format 9: short immediate group field t i short immediate operand (im9) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 format 9a: direct addressing field t r/w dr 1 offset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 format 10: do/redo field tni k bit 1514131211109876543210
data sheet march 2000 dsp1627 digital signal processor lucent technologies inc. 57 5 software architecture (continued) field descriptions table 41. t field table 42. d field table 43. at field table 44. s field table 45. f1 field table 46. x field specifies the type of instruction. t operation format 0000x goto ja 4 00010 short imm j, k, rb, re 9 00011 short imm r0, r1, r2, r3 9 00100 y = a1[l] f1 1 00101 z : at[l] f1 2a 00110 y f1 1 00111 at[l] = y f1 1a 01000 bit 0 = 0, at = r 7 01000 bit 0 = 1, atl = r 7 01001 bit 10 = 0, r = a0 7 01001 bit 10 = 1, r = a0l 7 01010 r = im16 8 01011 bit 10 = 0, r = a1 7 01011 bit 10 = 1, r = a1l 7 01100 y = r 7 01101 z : r 7 01110 do, redo 10 01111 r = y 7 1000x call ja 4 10010 ifc con f2 3 10011 if con f2 3 10100 y = y[l] f1 1 10101 z : y[l] f1 2 10110 x = y f1 1 10111 y[l] = y f1 1 11000 bit 0 = 0, branch indirect 5 11000 bit 0 = 1, f3 alu 3a 11001 y = a0 x = x f1 1 11010 cond. branch qualifier 6 11011 y = a1 x = x f1 1 11100 y = a0[l] f1 1 11101 z : y x = x f1 2 11110 bit 5 = 0, f4 alu (bmu) 3b 11110 bit 5 = 1, direct addressing 9a 11111 y = y x = x f1 1 specifies a destination accumulator. dregister 0 accumulator 0 1 accumulator 1 specifies transfer accumulator. at register 0 accumulator 1 1 accumulator 0 specifies a source accumulator. sregister 0 accumulator 0 1 accumulator 1 specifies the multiply/alu function. f1 operation 0000 ad = pp = x * y 0001 ad = as + pp = x * y 0010 p = x * y 0011 ad = as C pp = x * y 0100 ad = p 0101 ad = as + p 0110 nop 0111 ad = as C p 1000 ad = as | y 1001 ad = as ^ y 1010 as & y 1011 as C y 1100 ad = y 1101 ad = as + y 1110 ad = as & y 1111 ad = as C y specifies the addressing of rom data in two-operand multiply/alu instructions. specifies the high or low half of an accumulator or the y register in one-operand mul- tiply/alu instructions. x operation two-operand multiply/alu 0 * pt++ 1 * pt++i one-operand multiply/alu 0atl, yl 1ath, yh
data sheet dsp1627 digital signal processor march 2000 58 lucent technologies inc. 5 software architecture (continued) table 47. y field table 48. z field table 49. f2 field table 50. con field specifies the form of register indirect addressing with postmodification. y operation 0000 * r0 0001 * r0++ 0010 * r0-- 0011 * r0++j 0100 * r1 0101 * r1++ 0110 * r1-- 0111 * r1++j 1000 * r2 1001 * r2++ 1010 * r2-- 1011 * r2++j 1100 * r3 1101 * r3++ 1110 * r3-- 1111 * r3++j specifies the form of register indirect compound ad- dressing with postmodification. zoperation 0000 * r0zp 0001 * r0pz 0010 * r0m2 0011 * r0jk 0100 * r1zp 0101 * r1pz 0110 * r1m2 0111 * r1jk 1000 * r2zp 1001 * r2pz 1010 * r2m2 1011 * r2jk 1100 * r3zp 1101 * r3pz 1110 * r3m2 1111 * r3jk specifies the special function to be performed. f2 operation 0000 ad = as >> 1 0001 ad = as << 1 0010 ad = as >> 4 0011 ad = as << 4 0100 ad = as >> 8 0101 ad = as << 8 0110 ad = as >> 16 0111 ad = as << 16 1000 ad = p 1001 adh = ash + 1 1010 ad = ~as 1011 ad = rnd(as) 1100 ad = y 1101 ad = as + 1 1110 ad = as 1111 ad = C as specifies the condition for special functions and condi- tional control instructions. con condition con condition 00000 mi 01110 true 00001 pl 01111 false 00010 eq 10000 gt 00011 ne 10001 le 00100 lvs 10010 allt 00101 lvc 10011 allf 00110 mvs 10100 somet 00111 mvc 10101 somef 01000 heads 10110 oddp 01001 tails 10111 evenp 01010 c0ge 11000 mns1 01011 c0lt 11001 nmns1 01100 c1ge 11010 npint 01101 c1lt 11011 njint 11100 lock other codes reserved
data sheet march 2000 dsp1627 digital signal processor lucent technologies inc. 59 5 software architecture (continued) table 51. r field table 52. b field table 54. i field table 55. si field specifies the register for data move instructions. r register r register 000000 r0 100000 inc 000001 r1 100001 ins 000010 r2 100010 sdx2 000011 r3 100011 saddx 000100 j 100100 cloop 000101 k 100101 mwait 000110 rb 100110 saddx2 000111 re 100111 sioc2 001000 pt 101000 cbit 001001 pr 101001 sbit 001010 pi 101010 ioc 001011 i 101011 jtag 001100 p 101100 reserved 001101 pl 101101 reserved 001110 pllc 101110 reserved 001111 reserved 101111 reserved 010000 x 110000 a0 010001 y 110001 a0l 010010 yl 110010 a1 010011 auc 110011 a1l 010100 psw 110100 timerc 010101 c0 110101 timer0 010110 c1 110110 tdms2 010111 c2 110111 srta2 011000 sioc 111000 powerc 011001 srta 111001 reserved 011010 sdx 111010 ar0 011011 tdms 111011 ar1 011100 phifc 111100 ar2 011101 pdx0 111101 ar3 011110 reserved 111110 reserved 011111 ybase 111111 alf specifies the type of branch instruction (except software interrupt). b operation 000 return 001 ireturn 010 goto pt 011 call pt 1xx reserved table 53. dr field dr value register 0000 r0 0001 r1 0010 r2 0011 r3 0100 a0 0101 a0l 0110 a1 0111 a1l 1000 y 1001 yl 1010 p 1011 pl 1100 x 1101 pt 1110 pr 1111 psw specifies a register for short immediate data move in- structions. iregister 00 r0/j 01 r1/k 10 r2/rb 11 r3/re specifies when the conditional branch qualifier instruc- tion should be interpreted as a software interrupt in- struction. si operation 0 not a software interrupt 1 software interrupt
data sheet dsp1627 digital signal processor march 2000 60 lucent technologies inc. 5 software architecture (continued) ni field number of instructions to be loaded into the cache. zero implies redo operation. k field number of times the ni instructions in cache are to be executed. zero specifies use of value in cloop register. ja field 12-bit jump address. r/w field a zero specifies a write, *(o) = dr. a one specifies a read, dr = *(o). table 56. f3 field table 57. src2 field note: xx encodes the auxiliary register to be used. 00 (ar0), 01(ar1), 10 (ar2), or 11(ar3). specifies the operation in an f3 alu instruction. f3 operation 1000 ad = as[h, l] | {at, im16, p} 1001 ad = as[h, l] ^ {at, im16, p} 1010 as[h, l] & {at, im16, p} 1011 as[h, l] C {at, im16, p} 1101 ad = as[h, l] + {at, im16, p} 1110 ad = as[h, l] & {at, im16, p} 1111 ad = as[h, l] C {at, im16, p} specifies operands in an f3 alu instruction. src2 operands 00 asl, im16 10 ash, im16 01 as, at 11 as, p table 58. bmu encodings f4 ar operation 0000 00xx ad = as >> arm 0001 00xx ad = as << arm 0000 10xx ad = as >>> arm 0001 10xx ad = as <<< arm 1000 0000 ad = as >> as 1001 0000 ad = as << as 1000 1000 ad = as >>> as 1001 1000 ad = as <<< as 1100 0000 ad = as >> im16 1101 0000 ad = as << im16 1100 1000 ad = as >>> im16 1101 1000 ad = as <<< im16 0000 1100 ad = exp(as) 0001 11xx ad = norm(as, arm) 1110 0000 ad = extracts(as, im16) 0010 00xx ad = extracts(as, arm) 1110 0100 ad = extractz(as, im16) 0010 01xx ad = extractz(as, arm) 1110 1000 ad = insert(as, im16) 1010 10xx ad = insert(as, arm) 0111 0000 ad = as:aa0 0111 0001 ad = as:aa1
data sheet march 2000 dsp1627 digital signal processor lucent technologies inc. 61 6 signal descriptions figure 8. dsp1627 pinout by interface external memory interface io eramhi erom exm ab[15:0] db[15:0] rwn system interface or control i/o interface obe1 old1 ock1 do1 tdi tdo tck tms pods or old2 pstat or do2 pcsn or ock2 pobe or obe2 pbsel or sync2 pb2 or doen2 pibf or ibf2 pids or ild2 pb0 or ick2 pb1 or di2 pb3 or sadd2 pb[7:4] or iobit[3:o] dsp1627 rstb cko iack stop cki2 vec[3:0] or iobit[4:7] int[1:0] parallel host interface or serial interface #2 and control i/o interface ild1 di1 trap serial interface #1 ick1 ibf1 sync1 eramlo sadd1 doen1 jtag test interface 2 4 16 16 4 cki 5-4006 (c) figure 8 shows the pinout for the dsp1627. the signals can be separated into five interfaces as shown. these interfaces and the signals that comprise them are de- scribed below. 6.1 system interface the system interface consists of the clock, interrupt, and reset signals for the processor. rstb reset: negative assertion. a high-to-low transition causes the processor to enter the reset state. the auc, powerc, sioc, sioc2, phifc, pdx0, tdms, tdms2, timerc, timer0, sbit (upper byte), inc, ins (except obe, obe2, and pods status bits set), alf (upper 2 bits, await and lowpr), ioc, rb, and re registers are cleared. the mwait register is initialized to all 0s (zero wait-states) unless the exm pin is high and the int1 pin is low. in that case, the mwait register is initialized to all 1s (15 wait-states). reset clears iack, vec[3:0]/iobit[4:7], ibf, and ibf2. the dau condition flags are not affected by reset. iobit[7:0] are initialized as inputs. if any of the iobit pins are switched to outputs (by writing sbit), their initial value will be logic zero (see table 40, register settings after reset). upon negation of the signal, the processor begins exe- cution at location 0x0000 in the active memory map (see section 4.4, memory maps and wait-states).
data sheet dsp1627 digital signal processor march 2000 62 lucent technologies inc. 6 signal descriptions (continued) cki input clock: a mask-programmable option selects one of three possible input buffers for the cki pin (see sec- tion 7, mask-programmable options, and table 1, pin descriptions). the internal cki from the output of the selected input buffer can then drive the internal proces- sor clock directly (1x) or drive the on-chip pll (see sec- tion 4.13). the pll allows the cki input clock to be at a lower frequency than the internal processor clock. cki2 input clock 2: used with mask-programmable input clock options which require an external crystal or small signal differential across cki and cki2 (see table 1, pin descriptions). when the cmos option is selected, this pin should be tied to v ssa . stop stop input clock: negative assertion. a high-to-low transition synchronously stops all of the internal proces- sor clocks leaving the processor in a defined state. re- turning the pin high will synchronously restart the processor clocks to continue program execution from where it left off without any loss of state. this hardware feature has the same effect as setting the nock bit in the powerc register (see table 39). cko clock out: buffered output clock with options program- mable via the ioc register (see table 38). the selectable cko options (see tables 38 and 29) are as follows: n a free-running output clock at the frequency of the in- ternal processor clock; runs at the internal ring oscilla- tor frequency when slowcki is enabled. n a wait-stated clock based on the internal instruction cy- cle; runs at the internal ring oscillator frequency when slowcki is enabled. n a sequenced, wait-stated clock based on the emi se- quencer cycle; runs at the internal ring oscillator fre- quency when slowcki is enabled. n a free-running output clock that runs at the cki rate, in- dependent of the powerc register setting. this option is only available with the crystal and small-signal clock options. when the pll is selected, the cko frequency equals the input cki frequency regardless of how the pll is programmed. n a logic 0. n a logic 1. int[1:0] processor interrupts 0 and 1: positive assertion. hardware interrupt inputs to the dsp1627. each is en- abled via the inc register. when enabled and asserted, each cause the processor to vector to the memory loca- tion described in table 4. int1 is used in conjunction with exm to select the desired reset initialization of the mwait register (see table 36). when both int0 and rstb are asserted, all output and bidirectional pins (ex- cept tdo, which 3-states by jtag control) are put in a 3-state condition. vec[3:0] interrupt output vector: these four pins indicate which interrupt is currently being serviced by the device. table 4 shows the code associated with each interrupt condition. vec[3:0] are multiplexed with iobit[4:7]. iack interrupt acknowledge: positive assertion. iack signals when an interrupt is being serviced by the dsp1627. iack remains asserted while in an interrupt service routine, and is cleared when the ireturn instruc- tion is executed. trap trap signal: positive assertion. when asserted, the processor is put into the trap condition, which normally causes a branch to the location 0x0046. the hardware development system (hds) can configure the trap pin to cause an hds trap, which causes a branch to loca- tion 0x0003. although normally an input, the pin can be configured as an output by the hds. as an output, the pin can be used to signal an hds breakpoint in a multi- ple processor environment.
data sheet march 2000 dsp1627 digital signal processor lucent technologies inc. 63 6 signal descriptions (continued) 6.2 external memory interface the external memory interface is used to interface the dsp1627 to external memory and i/o devices. it sup- ports read/write operations from/to program and data memory spaces. the interface supports four external memory segments. each external memory segment can have an independent number of software-program- mable wait-states. one hardware address is decoded, and an enable line is provided, to allow glueless i/o in- terfacing. ab[15:0] external memory address bus: output only. this 16-bit bus supplies the address for read or write operations to the external memory or i/o. during exter- nal memory accesses, ab[15:0] retain the value of the last valid external access. db[15:0] external memory data bus: this 16-bit bidirectional data bus is used for read or write operations to the ex- ternal memory or i/o. rwn read/write not: when a logic 1, the pin indicates that the memory access is a read operation. when a logic 0, the memory access is a write operation. exm external memory select: input only. this signal is latched into the device on the rising edge of rstb. the value of exm latched in determines whether the internal rom is addressable in the instruction/coefficient mem- ory map. if exm is low, internal rom is addressable. if exm is high, only external rom is addressable in the instruction/coefficient memory map (see table 5, in- struction/coefficient memory maps). exm chooses be- tween map1 or map2 and between map3 or map4. erom external rom enable signal: negative assertion. when asserted, the signal indicates an access to external program memory (see table 5, instruction/co- efficient memory maps). this signal's leading edge can be delayed via the ioc register (see table 38). eramhi external ram high enable signal: negative asser- tion. when asserted, the signal indicates an access to external data memory addresses 0x8000 through 0xffff (see table 6, data memory map). this signal's leading edge can be delayed via the ioc register (see table 38). eramlo external ram low enable signal: negative asser- tion. when asserted, the signal indicates an access to external data memory addresses 0x4100 through 0x7fff (see table 6, data memory map). this signal's leading edge can be delayed via the ioc register (see table 38). io external i/o enable signal: negative assertion. when asserted, the signal indicates an access to external data memory addresses 0x4000 through 0x40ff (see table 6, data memory map). this memory segment is intended for memory-mapped i/o. this signal's leading edge can be delayed via the ioc register (see table 38).
data sheet dsp1627 digital signal processor march 2000 64 lucent technologies inc. 6 signal descriptions (continued) 6.3 serial interface #1 the serial interface pins implement a full-featured syn- chronous/asynchronous serial i/o channel. in addition, several pins offer a glueless tdm interface for multipro- cessing communication applications (see figure 5, mul- tiprocessor communications and connections). di1 data input: serial data is latched on the rising edge of ick1, either lsb or msb first, according to the sioc reg- ister msb field (see table 22). ick1 input clock: the clock for serial input data. in active mode, ick1 is an output; in passive mode, ick1 is an input, according to the sioc register ick field (see table 22). input has typically 0.7 v hysteresis. ild1 input load: the clock for loading the input buffer, sdx[in], from the input shift register isr. a falling edge of ild1 indicates the beginning of a serial input word. in active mode, ild1 is an output; in passive mode, ild1 is an input, according to the sioc register ild field (see table 22). input has typically 0.7 v hysteresis. ibf1 input buffer full: positive assertion. ibf1 is asserted when the input buffer, sdx[in], is filled. ibf1 is negated by a read of the buffer, as in a0 = sdx. ibf1 is also ne- gated by asserting rstb. do1 data output: the serial data output from the output shift register (osr), either lsb or msb first (according to the sioc register msb field). do1 changes on the rising edges of ock1. do1 is 3-stated when doen1 is high. doen1 data output enable: negative assertion. an input when not in the multiprocessor mode. do1 and sadd1 are enabled only if doen1 is low. doen1 is bidirection- al when in the multiprocessor mode (tdms register mode field set). in the multiprocessor mode, doen1 indicates a valid time slot for a serial output. ock1 output clock: the clock for serial output data. in active mode, ock1 is an output; in passive mode, ock1 is an input, according to the sioc register ock field (see ta- ble 22). input has typically 0.7 v hysteresis. old1 output load: the clock for loading the output shift reg- ister, osr, from the output buffer sdx[out]. a falling edge of old1 indicates the beginning of a serial output word. in active mode, old1 is an output; in passive, old1 is an input, according to the sioc register old field (see table 22). input has typically 0.7 v hysteresis. obe1 output buffer empty: positive assertion. obe1 is as- serted when the output buffer, sdx[out], is emptied (moved to the output shift register for transmission). it is cleared with a write to the buffer, as in sdx = a0. obe1 is also set by asserting rstb. sadd1 serial address: negative assertion. a 16-bit serial bit stream typically used for addressing during multiproces- sor communication between multiple dsp16xx devices. in multiprocessor mode, sadd1 is an output when the tdms time slot dictates a serial transmission; otherwise, it is an input. both the source and destination dsp can be identified in the transmission. sadd1 is always an output when not in multiprocessor mode and can be used as a second 16-bit serial output. see the dsp1611/17/18/27 digital signal processor informa- tion manual for additional information. sadd1 is 3-stat- ed when doen1 is high. when used on a bus, sadd1 should be pulled high through a 5 k w resistor. sync1 multiprocessor synchronization: typically used in the multiprocessor mode, a falling edge of sync1 indi- cates the first word (time slot 0) of a tdm i/o stream and causes the resynchronization of the active ild1 and old1 generators. sync1 is an output when the tdms register sync field is set (i.e., selects the master dsp and uses time slot 0 for transmit). as an input, sync1 must be tied low unless part of a tdm interface. when used as an output, sync1 = [ild1/old1]/8 or 16, depending on the setting of the syncsp field of the tdms register. when configured as described above, sync1 can be used to generate a slow clock for sio operations. input has typically 0.7 v hysteresis.
data sheet march 2000 dsp1627 digital signal processor lucent technologies inc. 65 6 signal descriptions (continued) 6.4 parallel host interface or serial interface #2 and control i/o interface this interface pin multiplexes a parallel host interface with a second serial i/o interface and a 4-bit i/o inter- face. the interface selection is made by writing the esio2 bit in the ioc register (see table 38 and section 4.1). the functions and signals for the second sio correspond exactly with those in sio #1. therefore, the pin descriptions below discuss only phif and bio pin functionality. pb[7:0] parallel i/o data bus: this 8-bit bidirectional bus is used to input data to, or output data from, the phif. note that pb[3:0] are pin multiplexed with sio2 func- tionality, and pb[7:4] are pin multiplexed with bio unit pins iobit[3:0] (see section 4.1). pcsn peripheral chip select not: negative assertion. pcsn is an input. while pcsn is low, the data strobes pids and pods are enabled. while pcsn is high, the dsp1627 ignores any activity on pids and pods. pbsel peripheral byte select: an input pin, configurable in software. selects the high or low byte of pdx0 available for host accesses. pstat peripheral status select: pstat is an input. when a logic 0, the phif will output the pdx0[out] register on the pb bus. when a logic 1, the phif will output the con- tents of the pstat register on pb[7:0]. pids parallel input data strobe: an input pin, software con- figurable to support both intel and motorola protocols. in intel mode: negative assertion. pids is pulled low by an external device to indicate that data is available on the pb bus. the dsp latches data on the pb bus on the rising edge (low-to-high transition) of pids or pcsn, whichever comes first. in motorola mode: pids(prwn*) functions as a read/ write strobe. the external device sets pids(prwn*) to a logic 0 to indicate that data is available on the pb bus (write operation by the external device). a logic 1 on pids(prwn*) indicates an external read operation by the external device. pods parallel output data strobe: an input pin, software configurable to support both intel and motorola proto- cols. in intel mode: negative assertion. when pods is pulled low by an external device, the dsp1627 places the con- tents of the parallel output register, pdx0, onto the pb bus. in motorola mode: software-configurable assertion level. the external device uses pods(pds * ) as its data strobe for both read and write operations. pibf parallel input buffer full: an output pin with positive assertion; configurable in software. this flag is cleared after reset, indicating an empty input buffer pdx0[in]. pibf is set immediately after the rising edge of pids or pcsn, indicating that data has been latched into the pdx0[in] register. when the dsp1627 reads the con- tents of this register, emptying the buffer, the flag is cleared. configured in software, pibf may become the logical or of the pibf and pobe flags. pobe parallel output buffer empty: an output pin with pos- itive assertion; configurable in software. this flag is set after reset, indicating an empty output buffer pdx0[out]. pobe is set immediately after the rising edge of pods or pcsn, indicating that the data in pdx0[out] has been driven onto the pb bus. when the dsp1627 writes to pdx0[out], filling the buffer, this flag is cleared. 6.5 control i/o interface this interface is used for status and control operations provided by the bit i/o unit of the dsp1627. it is pin mul- tiplexed with the phif and vec[3:0] pins (see section 4.1). setting the esio2 and ebioh bits in the ioc regis- ter provides a full 8-bit bio interface at the associated pins. iobit[7:0] i/o bits [7:0]: each of these bits can be independently configured as either an input or an output. as outputs, they can be independently set, toggled, or cleared. as inputs, they can be tested independently or in combina- tions for various data patterns. * motorola mode signal name.
data sheet dsp1627 digital signal processor march 2000 66 lucent technologies inc. 6 signal descriptions (continued) 6.6 jtag test interface the jtag test interface has features that allow pro- grams and data to be downloaded into the dsp via four pins. this provides extensive test and diagnostic capa- bility. in addition, internal circuitry allows the device to be controlled through the jtag port to provide on-chip in-circuit emulation. lucent technologies provides hardware and software tools to interface to the on-chip hds via the jtag port. note: the dsp1627 provides all jtag/ ieee 1149.1 standard test capabilities including boundary scan. see the dsp1611/17/18/27 digital signal processor information manual for additional in- formation on the jtag test interface. tdi test data input: jtag serial input signal. all serial- scanned data and instructions are input on this pin. this pin has an internal pull-up resistor. tdo test data output: jtag serial output signal. serial- scanned data and status bits are output on this pin. tms test mode select: jtag mode control signal that, when combined with tck, controls the scan operations. this pin has an internal pull-up resistor. tck test clock: jtag serial shift clock. this signal clocks all data into the port through tdi, and out of the port through tdo, and controls the port by latching the tms signal inside the state-machine controller.
data sheet march 2000 dsp1627 digital signal processor lucent technologies inc. 67 7 mask-programmable options the dsp1627 contains a rom that is mask-programmable. the selection of several programmable features is made when a custom rom is encoded. these features select the input clock options, the instruction/coefficient memory map option, and the hardware emulation or rom security option, as summarized in table 59. 7.1 input clock options for all input options, the input clock cki can run at some fraction of the internal clock frequency by setting the pll multiplication factors appropriately (see section 4.12, clock synthesis). when the pll is bypassed, the input clock cki frequency is the internal clock frequency. if the mask option for using an external crystal is chosen, the internal oscillator may be used as a noninverting input buffer by supplying a cmos level to the cki pin and leaving the cki2 pin open. 7.2 memory map options the dsp1627 offers a dsp1627x36 or a dsp1627x32 where the difference is in the instruction/coefficient memory maps. the dsp1627x36 contains 36 kwords of internal rom (irom), but it doesnt support the use of irom and external rom (erom) in the same memory map. the dsp1627x32 supports the use of only 32 kwords of irom with 16 kwords of erom in the same memory map. see section 4.4 memory maps and wait-states for further de- scription. 7.3 rom security options the dsp1600 hardware development system (hds) provides on-chip in-circuit emulation and requires that the re- locatable hds code be linked to the application code. this code's object file is called 1627hds.v # , where # is a unique version identifier. refer to the dsp1627-st software tools release for more specific information. if on-chip in-circuit emulation is desired, a nonsecure rom must be chosen. if rom security is desired with the dsp1627, the hds cannot be used. to provide testing of the internal rom contents on a secure rom device, a cyclic redundancy check (crc) program is called by and linked with the user's source code. the crc code resides in the first 4 kwords of rom. see the dsp1600 support tools manual for more detailed information. table 59. dsp1627 rom options features options comments input clock cmos level small signal crystal 2.7 v, 3.0 v, and 5.0 v. 2.7 v, 3.0 v, and 5.0 v. 2.7 v, 3.0 v, and 5.0 v. memory map dsp1627x36 dsp1627x32 36 kwords irom, no erom in map1 or map3. 32 kwords irom, 16 kwords erom in map1 and map3. rom security nonsecure secure specify and link 1627hds.v # * , allows emulation. specify and link crc16.v # ? , no emulation capability. * 1627hds.v # (# indicates the current version number) is the relocatable hds object code. it uses approximately 140 words and must reside in the first 4 kwords of rom. ? crc16.v # is the cyclic redundancy check object code. it uses approximately 75 words and must reside in the first 4 kwords of rom. see the dsp1600 support tools manual for detailed information.
data sheet dsp1627 digital signal processor march 2000 68 lucent technologies inc. 8 device characteristics 8.1 absolute maximum ratings stresses in excess of the absolute maximum ratings can cause permanent damage to the device. these are abso- lute stress ratings only. functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of the data sheet. exposure to absolute maximum ratings for extended periods can adversely affect device reliability. external leads can be bonded and soldered safely at temperatures of up to 300 c. voltage range on v dd with respect to ground using devices designed for 5 v operation .............C0.5 v to +7 v voltage range on v dd with respect to ground using devices designed for 3 v operation ..........C0.5 v to +4.6 v voltage range on any pin ............................................................................................ .v ss C 0.5 v to v dd + 0.5 v power dissipation.............................................................................................................. .................................. 1 w ambient temperature range ...................................................................................................... ... C40 c to +85 c storage temperature range .................................................................................................................... C 65 c to +150 c 8.2 handling precautions all mos devices must be handled with certain precautions to avoid damage due to the accumulation of static charge. although input protection circuitry has been incorporated into the devices to minimize the effect of this static buildup, proper precautions should be taken to avoid exposure to electrostatic discharge during handling and mount- ing. lucent technologies employs a human-body model for esd susceptibility testing. since the failure voltage of electronic devices is dependent on the current, voltage, and hence, the resistance and capacitance, it is important that standard values be employed to establish a reference by which to compare test data. values of 100 pf and 1500 w are the most common and are the values used in the lucent technologies human-body model test circuit. the breakdown voltage for the dsp1627 is greater than 2000 v. 8.3 recommended operating conditions the ratio of the instruction cycle rate to the input clock frequency is 1:1 without the pll (referred to as 1x operation) and m/(2n) with the pll selected (see section 4.12). device speeds greater than 50 mips do not support 1x operation; use the pll. table 60. recommended operating conditions maximum instruction rate (mips) device speed input clock package supply voltage v dd (v) ambient temperature t a ( c) min max min max 50 20 ns cmos, small-signal, crystal bqfp or tqfp 2.7 3.3 C40 85 80 12.5 ns cmos, small-signal, crystal bqfp or tqfp 2.7 3.3 C40 85 100 10 ns cmos, small-signal, crystal bqfp or tqfp 3.0 3.6 C40 85 70 14 ns cmos, small-signal, crystal bqfp or tqfp 4.75 5.25 C40 85 90 11 ns cmos, small-signal, crystal bqfp or tqfp 4.75 5.25 C40 85
data sheet march 2000 dsp1627 digital signal processor lucent technologies inc. 69 8 device characteristics (continued) 8.4 package thermal considerations the recommended operating temperature specified above is based on the maximum power, package type, and maximum junction temperature. the following equations describe the relationship between these parameters. if the applications' maximum power is less than the worst-case value, this relationship determines a higher maximum am- bient temperature or the maximum temperature measured at top dead center of the package. t a = t j C p x q ja t tdc = t j C p x q j-tdc where t a is the still-air ambient temperature and t tdc is the temperature measured by a thermocouple at the top dead center of the package. maximum junction temperature (t j ) in 100-pin bqfp ................................................................................. 125 c 100-pin bqfp maximum thermal resistance in still-air-ambient ( q ja ) ..................................................... 55 c/w 100-pin bqfp maximum thermal resistance, junction to top dead center ( q j-tdc ) ............................... 12 c/w maximum junction temperature (t j ) in 100-pin tqfp ................................................................................. 125 c 100-pin tqfp maximum thermal resistance in still-air-ambient ( q ja ) ..................................................... 30 c/w 100-pin tqfp maximum thermal resistance, junction to top dead center ( q j-tdc ) ................................. 6 c/w warning: due to package thermal constraints, proper precautions in the user's application should be tak- en to avoid exceeding the maximum junction temperature of 125 c. otherwise, the device will be affected adversely.
data sheet dsp1627 digital signal processor march 2000 70 lucent technologies inc. 9 electrical characteristics and requirements the following electrical characteristics are preliminary and are subject to change. electrical characteristics refer to the behavior of the device under specified conditions. electrical requirements refer to conditions imposed on the user for proper operation of the device. the parameters below are valid for the conditions described in section 8.3, recommended operating conditions. table 61. electrical characteristics and requirements parameter symbol min max unit input voltage: low v il C0.3 0.3 * v dd v high v ih 0.7 * v dd v dd + 0.3 v input current (except tms, tdi): low (v il = 0 v, v dd = 5.25 v) i il C5 m a high (v ih = 5.25 v, v dd = 5.25 v) i ih 5 m a input current (tms, tdi): low (v il = 0 v, v dd = 5.25 v) i il C100 m a high (v ih = 5.25 v, v dd = 5.25 v) i ih 5 m a output low voltage: low (i ol = 2.0 ma) v ol 0.4v low (i ol = 50 m a) v ol 0.2v output high voltage: high (i oh = C2.0 ma) v oh v dd C 0.7 v high (i oh = C50 m a) v oh v dd C 0.2 v output 3-state current: low (v dd = 5.25 v, v il = 0 v) i ozl C10 m a high (v dd = 5.25 v, v ih = 5.25 v) i ozh 10 m a input capacitance ci 5 pf table 62. electrical requirements for mask-programmable input clock options parameter symbol min max unit cki cmos level input voltage: low v il C0.3 0.3 * v dd v high v ih 0.7 * v dd v dd + 0.3 v small-signal peak-to-peak voltage * * the small-signal buffer must be used in single-ended mode where an ac waveform (sine or square) is applied to cki and a dc vol tage approx- imately equal to the average value of cki is applied to cki2, as shown in the figure below. the maximum allowable ripple on cki 2 is 100 mv. vpp 0.6 v (on cki) small-signal input duty cycle ? ? duty cycle for a sine wave is defined as the percentage of time during each clock cycle that the voltage on cki exceeds the vo ltage on cki2. dcyc 45 55 % small-signal input voltage range (pins: cki, cki2) vin 0.2 * v dd 0.6 * v dd v small-signal buffer frequency range fss 35 mhz frequency range of fundamental mode or overtone crystal fx 5 25 mhz series resistance of fundamental mode or overtone crystal (pins: cki, cki2) rs 40 w mutual capacitance of crystal (includes board stray capacitance) c0 7 pf cki cki2
data sheet march 2000 dsp1627 digital signal processor lucent technologies inc. 71 9 electrical characteristics and requirements (continued) additional electrical requirements with crystal option: see section 13, crystal electrical characteristics and requirements. table 63. pll electrical specifications, vco frequency ranges parameter symbol min max unit vco frequency range (v dd = 3 v 10%) * * the m and n counter values in the pllc register must be set so that the vco will operate in the appropriate range (see table 6 3). choose the lowest value of n and then the appropriate value of m for f internal clock = f cki x (m/(2n)) = f vco /2. f vco 50 160 mhz vco frequency range (v dd = 3.0 v C 3.6 v)* f vco 50 200 mhz vco frequency range (v dd = 5 v 5%)* f vco 70 180 mhz input jitter at cki 200 ps-rms table 64. pll electrical specifications and pllc register settings mv dd pllc13 (icp) pllc12 (sel5v) pllc[11:8] (lf[3:0]) typical lock-in time ( m m m m s) * * lock-in time represents the time following assertion of the pllen bit of the pllc register during which the pll output clock i s unstable. the dsp must operate from the 1x cki input clock or from the slow ring oscillator while the pll is locking. completion of the lock- in interval is indicated by assertion of the lock flag. 2324 2.7 v C 3.6 v 1 0 1011 30 2122 2.7 v C 3.6 v 1 0 1010 30 1920 2.7 v C 3.6 v 1 0 1001 30 1618 2.7 v C 3.6 v 1 0 1000 30 1215 2.7 v C 3.6 v 1 0 0111 30 811 2.7 v C 3.6 v 1 0 0110 30 27 2.7 v C 3.6 v 1 0 0100 30 1920 5 v 5% 1 1 1110 30 1718 5 v 5% 1 1 1101 30 16 5 v 5% 1 1 1100 30 1415 5 v 5% 1 1 1011 30 1213 5 v 5% 1 1 1010 30 1011 5 v 5% 1 1 1001 30 89 5 v 5% 1 1 1000 30 75 v 5% 1 1 0111 30 56 5 v 5% 1 1 0110 30 24 5 v 5% 1 1 0101 30
data sheet dsp1627 digital signal processor march 2000 72 lucent technologies inc. 9 electrical characteristics and requirements (continued) figure 9. plot of v oh vs. i oh under typical operating conditions figure 10. plot of v ol vs. i ol under typical operating conditions 0 10203040 51525354550 device under test i oh (ma) v oh (v) v dd C 0.1 v dd C 0.2 v dd C 0.3 v dd C 0.4 v dd i oh v oh 5-4007 (f).a 5-4008 (f).b device under test i ol v ol 0.4 0.3 0.2 0.1 0 v ol (v) 0 5 10 15 20 25 30 35 40 45 50 i ol (ma)
data sheet march 2000 dsp1627 digital signal processor lucent technologies inc. 73 9 electrical characteristics and requirements (continued) 9.1 power dissipation power dissipation is highly dependent on dsp program activity and the frequency of operation. the typical power dissipation listed is for a selected application. the following electrical characteristics are preliminary and are subject to change. * t = cki clock cycle for 1x input clock option or t = cki clock cycle divided by m/(2n) for pll clock option (see section 4.1 2). ? t l = pll lock time (see table 64). table 65. power dissipation and wake-up latency operating mode (unused inputs at vdd or vss) typical power dissipation (mw) wake-up latency i/o units on powerc[7:4] = 0x0 i/o units off powerc[7:4] = 0xf (pll not used during wake state) (pll used during wake state) 5 v 3 v 5 v 3 v 5 v 3 v 5 v 3 v normal operation ioc = 0x0180 pll disabled cki & cko = 40 mhz cmos 220 74 214 72 crystal oscillator 241 80 235 78 small signal 223 76 217 74 cki & cko = 0 mhz cmos 0.19 0.067 0.19 0.067 small signal 3.0 1.1 3.0 1.1 normal operation ioc = 0x0180 pll enabled pllc = 0xfc0e cki = 10 mhz cko = 40 mhz cmos 228 77 222 75 crystal oscillator 249 83 243 81 small signal 231 78 225 77 power management modes cko = 40 mhz standard sleep, external interrupt alf[15] = 1, ioc = 0x0180 pll disabled during sleep cmos 25.2 8.4 17.8 5.6 3t* 3t* + t l ? crystal oscillator 46.2 14.0 38.8 12.0 3t* 3t* + t l ? small signal 28.0 9.8 20.8 7.2 3t* 3t* + t l ? standard sleep, external interrupt alf[15] = 1, ioc = 0x0180 pll enabled during sleep cmos 33.2 10.9 25.8 7.5 3t* crystal oscillator 54.0 17.1 46.0 14.0 3t* small signal 36.0 12.4 28.8 9.2 3t* sleep with slow internal clock crystal/small signal enabled powerc[15:14] = 01, alf[15] = 1, ioc = 0x0180 pll disabled during sleep cmos 1.4 0.4 1.1 0.3 1.5 m s5.0 m s1.5 m s + t l 5.0 m s + t l crystal oscillator 21.9 6.2 21.8 6.1 1.5 m s5.0 m s1.5 m s + t l 5.0 m s + t l small signal 3.9 2.1 3.8 2.0 1.5 m s5.0 m s1.5 m s + t l 5.0 m s + t l
data sheet dsp1627 digital signal processor march 2000 74 lucent technologies inc. 9 electrical characteristics and requirements (continued) * t = cki clock cycle for 1x input clock option or t = cki clock cycle divided by m/(2n) for pll clock option (see section 4.12) . ? t l = pll lock time (see table 64). the power dissipation listed is for internal power dissipation only. total power dissipation can be calculated on the basis of the application by adding c x v dd /2 x f for each output, where c is the additional load capacitance and f is the output frequency. table 65. power dissipation and wake-up latency (continued) operating mode (unused inputs at vdd or vss) typical power dissipation (mw) wake-up latency i/o units on powerc[7:4] = 0x0 i/o units off powerc[7:4] = 0xf (pll not used during wake state) (pll used during wake state) 5 v 3 v 5 v 3 v 5 v 3 v 5 v 3 v sleep with slow internal clock crystal/small signal enabled powerc[15:14] = 01, alf[15] = 1, ioc = 0x0180 pll enabled during sleep cmos 8.3 3.0 7.5 2.7 1.5 m s5.0 m s crystal oscillator 27.5 9.9 24.5 8.8 1.5 m s5.0 m s small signal 10.0 4.5 10.0 4.0 1.5 m s5.0 m s sleep with slow internal clock crystal/small signal disabled powerc[15:14] = 11, alf[15] = 1, ioc = 0x0180 pll disabled during sleep crystal oscillator 0.67 0.24 0.56 0.16 20 ms 20 s + t l ? small signal 0.67 0.24 0.56 0.16 20 m s 20 s + t l ? software stop powerc[15:12] = 0011 pll disabled during stop cmos 0.19 0.067 0.19 0.067 3t* 3t* + t l ? software stop powerc[15:12] = 1111 pll disabled during stop crystal oscillator 0.19 0.067 0.19 0.067 20 ms 20 s +t l ? small signal 0.19 0.067 0.19 0.067 20 m s 20 s + t l ? hardware stop (stop = v ss ) powerc[15:12] = 0000 pll disabled during stop cmos 0.19 0.067 0.19 0.067 3t* crystal oscillator 20.0 6.0 20.0 6.0 3t* small signal 3.0 1.1 3.0 1.1 3t* hardware stop (stop = v ss ) powerc[15:12] = 0000 pll enabled during stop cmos 5.6 2.4 5.6 2.4 3t* 3t* crystal oscillator 25.6 8.4 25.6 8.4 3t* 3t* small signal 8.6 3.5 8.6 3.5 3t* 3t*
data sheet march 2000 dsp1627 digital signal processor lucent technologies inc. 75 9 electrical characteristics and requirements (continued) power dissipation due to the input buffers is highly dependent on the input voltage level. at full cmos levels, es- sentially no dc current is drawn. however, for levels between the power supply rails, especially at or near the thresh- old of v dd /2, high currents can flow. although input and i/o buffers may be left untied (since the input voltage levels of the input and i/o buffers are designed to remain at full cmos levels when not driven by the dsp), it is still rec- ommended that unused input and i/o pins be tied to v ss or v dd through a 10 k w resistor to avoid application am- biguities. further, if i/o pins are tied high or low, they should be pulled fully to v ss or v dd . warning: the device needs to be clocked for at least six cki cycles during reset after powerup. otherwise, high currents may flow. 10 timing characteristics for 5 v operation the following timing characteristics and requirements are preliminary information and are subject to change. timing characteristics refer to the behavior of the device under specified conditions. timing requirements refer to conditions imposed on the user for proper operation of the device. all timing data is valid for the following conditions: t a = C40 c to +85 c (see section 8.3.) v dd = 5 v 5%, v ss = 0 v (see section 8.3.) capacitance load on outputs (c l ) = 50 pf, except for cko, where c l = 20 pf. output characteristics can be derated as a function of load capacitance (c l ). all outputs: 0.03 ns/pf dt/dc l 0.06 ns/pf for 10 c l 100 pf at v ih for rising edge and at v il for falling edge. for example, if the actual load capacitance is 30 pf instead of 50 pf, the derating for a rising edge is (30 C 50) pf x 0.06 ns/pf = 1.2 ns less than the specified rise time or delay that includes a rise time. test conditions for inputs: n rise and fall times of 4 ns or less n timing reference levels for delays = v ih , v il test conditions for outputs (unless noted otherwise): n c load = 50 pf; except for cko, where c load = 20 pf n timing reference levels for delays = v ih , v il n 3-state delays measured to the high-impedance state of the output driver for the timing diagrams, see table 62 for input clock requirements. unless otherwise noted, cko in the timing diagrams is the free-running cko.
data sheet dsp1627 digital signal processor march 2000 76 lucent technologies inc. 10 timing characteristics for 5 v operation (continued) 10.1 dsp clock generation * see table 62 for input clock electrical requirements. ? free-running clock. ? wait-stated clock (see table 38). w = number of wait-states. figure 11. i/o clock timing diagram * device speeds greater than 50 mips do not support 1x operation. use the pll. ? device is fully static, t1 is tested at 100 ns for 1x input clock option, and memory hold time is tested at 0.1 s. * t = internal clock period, set by cki or by cki and the pll parameters. table 66. timing requirements for input clock abbreviated reference parameter 14 ns and 11 ns * min max unit t1 clock in period (high to high) 20 ? ns t2 clock in low time (low to high) 10 ns t3 clock in high time (high to low) 10 ns table 67. timing characteristics for input clock and output clock abbreviated reference parameter 14 ns 11 ns unit min max min max t4 clock out high delay 10 8 ns t5 clock out low delay (high to low) 10 8 ns t6 clock out period (low to low) t* t* ns t6a clock out period with slowcki bit set in powerc register (low to low) 0.74 1.6 0.74 1.6 m s 5-4009 (f).a t4 t1 t2 1x cki* t5 cko ? t3 t6, t6a cko ? external memory cycle w = 1
data sheet march 2000 dsp1627 digital signal processor lucent technologies inc. 77 10 timing characteristics for 5 v operation (continued) 10.2 reset circuit the dsp1627 has a powerup reset circuit that automatically clears the jtag controller upon powerup. if the supply voltage falls below v dd min* and a reset is required, the jtag controller must be reseteven if the jtag port isnt being usedby applying six low-to-high clock edges on tck with tms held high, followed by the usual rstb and cki reset sequence. figure 12 shows two separate events: an initial powerup and a powerup following a drop in the power supply voltage. * see table 60, recommended operating condiitons. notes: see table 62 for cki electrical requirements and table 71 for tck timing requirements. when both int0 and rstb are asserted, all output and bidirectional pins (except tdo, which 3-states by jtag control) are put in a 3-state condition. with rstb asserted and int0 not asserted, erom, eramhi, eramlo, io, dsel, and rwn outputs remain high, and cko remai ns a free-running clock. tms and tdi signals have internal pull-up devices. figure 12. powerup reset and chip reset timing diagram * with external components as specified in table 62. ?t tck = t12 = tck period. see table 71 for tck timing requirements. table 68. timing requirements for powerup reset and chip reset abbreviated reference parameter min max unit t8 reset pulse (low to high) 6t ns t9 v dd ramp 10 ms t146 v dd min to rstb low cmos crystal* small-signal 2t 20 20 ns ms m s t151 tms high 6 * t tck ? ns t152 jtag reset to cmos rstb low crystal* small-signal 2t 20 ms C 6 * t tck if 6 * t tck < 20 ms 0 if 6 * t tck 3 20 ms 20 s C 6 * t tck if 6 * t tck < 20 s 0 if 6 * t tck 3 20 s ns t153 rstb rise (low to high) 95 ns 5-2253 (f).a t10 t11 t10 t11 t9 t146 t8 t9 t151 t152 t8 v dd ramp cki tck tms rstb pins v oh v ol v ih v il v ih 0.4 v v dd min v dd min 0.4 v t153 t153
data sheet dsp1627 digital signal processor march 2000 78 lucent technologies inc. 10 timing characteristics for 5 v operation (continued) note: the device needs to be clocked for at least six cki cycles during reset after powerup. otherwise, high cur- rents may flow. 10.3 reset synchronization * see table 62 for input clock electrical requirements. note: cko 1 and cko 2 are two possible cko states before reset. cko is free-running. figure 13. reset synchronization timing table 69. timing characteristics for powerup reset and chip reset abbreviated reference parameter min max unit t10 rstb disable time (low to 3-state) 100 ns t11 rstb enable time (high to valid) 100 ns table 70. timing requirements for reset synchronization timing abbreviated reference parameter min max unit t126 reset setup (high to high) 1.5 t/2 C 5 ns 5-4011 (f).a cki * v ih v il t126 t5 + 2 x t6 rstb v ih v il v ih v il cko v ih v il cko
data sheet march 2000 dsp1627 digital signal processor lucent technologies inc. 79 10 timing characteristics for 5 v operation (continued) 10.4 jtag i/o specifications figure 14. jtag timing diagram table 71. timing requirements for jtag input/output abbreviated reference parameter min max unit t12 tck period (high to high) 50 ns t13 tck high time (high to low) 22.5 ns t14 tck low time (low to high) 22.5 ns t15 tms setup time (valid to high) 7.5 ns t16 tms hold time (high to invalid) 2 ns t17 tdi setup time (valid to high) 7.5 ns t18 tdi hold time (high to invalid) 2 ns table 72. timing characteristics for jtag input/output abbreviated reference parameter min max unit t19 tdo delay (low to valid) 19 ns t20 tdo hold (low to invalid) 0 ns t12 t14 t13 t15 t16 t17 t18 t19 t20 tck tms tdi tdo v ih v il v ih v il v ih v il v oh v ol t155 t156 5-4017 (f)
data sheet dsp1627 digital signal processor march 2000 80 lucent technologies inc. 10 timing characteristics for 5 v operation (continued) 10.5 interrupt * cko is free-running. ? iack assertion is guaranteed to be enclosed by vec[3:0] assertion. figure 15. interrupt timing diagram note: interrupt is asserted during an interruptible instruction and no other pending interrupts. note: interrupt is asserted during an interruptible instruction and no other pending interrupts. table 73. timing requirements for interrupt abbreviated reference parameter min max unit t21 interrupt setup (high to low) 15 ns t22 int assertion time (high to low) 2t ns table 74. timing characteristics for interrupt abbreviated reference parameter min max unit t23 iack assertion time (low to high) t/2 + 7.5 ns t24 vec assertion time (low to high) 9.5 ns t25 iack invalid time (low to low) 7.5 ns t26 vec invalid time (low to low) 9.5 ns 5-4018 (f) cko * int[1:0] t21 v oh v ol v ih v il t22 iack ? v oh v ol vec[3:0] v oh v ol t23 t24 t25 t26
data sheet march 2000 dsp1627 digital signal processor lucent technologies inc. 81 10 timing characteristics for 5 v operation (continued) 10.6 bit input/output (bio) figure 16. write outputs followed by read inputs (cbit = immediate; a1 = sbit) figure 17. write outputs and test inputs (cbit = immediate) table 75. timing requirements for bio input read abbreviated reference parameter min max unit t27 iobit input setup time (valid to high) 12 ns t28 iobit input hold time (high to invalid) 0 ns table 76. timing characteristics for bio output abbreviated reference parameter min max unit t29 iobit output valid time (low to valid) 7.5 ns t144 iobit output hold time (low to invalid) 1 ns table 77. timing requirements for bio input test abbreviated reference parameter min max unit t141 iobit input setup time (valid to low) 12 ns t142 iobit input hold time (low to invalid) 0 ns cko iobit (input) t28 t27 valid output v i h v i l v o h v o l v o h v o l data input t29 t144 iobit (output) 5-4019 (f).a cko iobit (input) t142 t141 valid output v oh C v o lC test input t29 t144 iobit (output) v oh C v o lC v ih C v i lC 5-4019 (f).b
data sheet dsp1627 digital signal processor march 2000 82 lucent technologies inc. 10 timing characteristics for 5 v operation (continued) 10.7 external memory interface the following timing diagrams, characteristics, and requirements do not apply to interactions with delayed external memory enables unless so stated. see the dsp1611/17/18/27 digital signal processor information manual for a detailed description of the external memory interface including other functional diagrams. * w = number of wait-states. figure 18. enable transition timing table 78. timing characteristics for external memory enables (erom, eramhi, io, eramlo) abbreviated reference parameter min max unit t33 cko to enable active (low to low) 0 7 ns t34 cko to enable inactive (low to high) C1 6 ns table 79. timing characteristics for delayed external memory enables (ioc = 0x000f) abbreviated reference parameter min max unit t33 cko to delayed enable active (low to low) t/2 C 2 t/2 + 7 ns cko enable t34 t33 w * = 0 v oh v ol v oh v ol 5-4020 (f).b
data sheet march 2000 dsp1627 digital signal processor lucent technologies inc. 83 10 timing characteristics for 5 v operation (continued) * w = number of wait-states. figure 19. external memory data read timing diagram table 80. timing characteristics for external memory access abbreviated reference parameter min max unit t127 enable width (low to high) t(1 + w) C 4 ns t128 address valid (enable low to valid) 2 ns table 81. timing requirements for external memory read (erom, eramhi, io, eramlo) abbreviated reference parameter 14 ns 11 ns unit min max min max t129 read data setup (valid to enable high) 12 11 ns t130 read data hold (enable high to hold) 0 0 ns t150 external memory access time (valid to valid) t(1 + w) C 13 t(1 + w) C 12 ns v ih v il db cko ab v oh v ol t128 read address enable v oh v ol v oh v ol (mwait = 0 x 2222) w* = 2 t127 t129 t130 read data t150 5-4021 (f).a
data sheet dsp1627 digital signal processor march 2000 84 lucent technologies inc. 10 timing characteristics for 5 v operation (continued) * w = number of wait-states. figure 20. external memory data write timing diagram table 82. timing characteristics for external memory data write (all enables) abbreviated reference parameter 14 ns 11 ns unit min max min max t131 write overlap (enable low to 3-state) 0 0 ns t132 rwn advance (rwn high to enable high) 0 0 ns t133 rwn delay (enable low to rwn low) 00ns t134 write data setup (data valid to rwn high) t(1 + w)/2 C 3 t(1 + w)/2 C 2 ns t135 rwn width (low to high) t(1 + w) C 5.5 t(1 + w) C 5.5 ns t136 write address setup (address valid to rwn low) 00ns eramlo erom cko ab rwn db write address read address v oh v ol v oh v ol v oh v ol v oh v ol v oh v ol write data read w* = 1 t131 t132 t134 t133 t135 t136 (mwait = 0x1002) w* = 2 v oh v ol 5-4022 (f).a
data sheet march 2000 dsp1627 digital signal processor lucent technologies inc. 85 10 timing characteristics for 5 v operation (continued) * w = number of wait-states. figure 21. write cycle followed by read cycle table 83. timing characteristics for write cycle followed by read cycle abbreviated reference parameter min max unit t131 write overlap (enable low to 3-state) 0 ns t137 write data 3-state (rwn high to 3-state) 2 ns t138 write data hold (rwn high to data hold) 0 ns t139 write address hold (rwn high to address hold) 0 ns eramlo cko ab rwn write address read address v oh v ol v oh v ol v oh v ol v oh v ol w* = 1 t137 (mwait = 0x1002) w* = 2 erom v oh v ol db write read v oh v ol t138 t139 t131 5-4023 (f).a
data sheet dsp1627 digital signal processor march 2000 86 lucent technologies inc. 10 timing characteristics for 5 v operation (continued) 10.8 phif specifications for the phif, "read" means read by the external user (output by the dsp); "write" is similarly defined. the 8-bit reads/ writes are identical to one-half of a 16-bit access. figure 22. phif intel mode signaling (read and write) timing diagram * this timing diagram for the phif port shows accesses using the pcsn signal to initiate and complete a transaction. the transac tions can also be initiated and completed with the pids and pods signals. an output transaction (read) is initiated by pcsn or pods going low, whichever co mes last. for example, the timing requirements referenced to pcsn going low, t45 and t49, should be referenced to pods going low, if pods goes low aft er pcsn. an output transaction is completed by pcsn or pods going high, whichever comes first. an input transaction is initiated by pcsn or pids g oing low, whichever comes last. an input transaction is completed by pcsn or pids going high, whichever comes first. all requirements referenced to pcsn apply to pids or pods, if pids or pods is the controlling signal. * this timing diagram for the phif port shows accesses using the pcsn signal to initiate and complete a transaction. the transac tions can also be initiated and completed with the pids and pods signals. an output transaction (read) is initiated by pcsn or pods going low, whichever co mes last. for example, the timing requirements referenced to pcsn going low, t45 and t49, should be referenced to pods going low, if pods goes low aft er pcsn. an output transaction is completed by pcsn or pods going high, whichever comes first. an input transaction is initiated by pcsn or pids g oing low, whichever comes last. an input transaction is completed by pcsn or pids going high, whichever comes first. all requirements referenced to pcsn apply to pids or pods, if pids or pods is the controlling signal. table 84. timing requirements for phif intel mode signaling abbreviated reference parameter min max unit t41 pods to pcsn setup (low to low) 0 ns t42 pcsn to pods hold (high to high) 0 ns t43 pids to pcsn setup (low to low) 0 ns t44 pcsn to pids hold (high to high) 0 ns t45* pstat to pcsn setup (valid to low) 4.5 ns t46* pcsn to pstat hold (high to invalid) 0 ns t47* pbsel to pcsn setup (valid to low) 4.5 ns t48* pcsn to pbsel hold (high to invalid) 0 ns t51* pb write to pcsn setup (valid to high) 7.5 ns t52* pcsn to pb write hold (high to invalid) 4 ns table 85. timing characteristics for phif intel mode signaling abbreviated reference parameter min max unit t49* pcsn to pb read (low to valid) 13 ns t50* pcsn to pb read hold (high to invalid) 3 ns pcsn t41 t42 t43 t45 t46 t49 t50 16-bit read 16-bit write pods pids pbsel pstat pb[7:0] t47 t51 t52 t48 t44 5-4036 (f) t154 v ih C v il C v ih C v il C v ih C v il C v ih C v il C v ih C v il C v ih C v il C
data sheet march 2000 dsp1627 digital signal processor lucent technologies inc. 87 10 timing characteristics for 5 v operation (continued) figure 23. phif intel mode signaling (pulse period and flags) timing diagram * t53 should be referenced to the rising edge of pcsn or pods, whichever comes first. t54 should be referenced to the rising edge of pcsn or pids, whichever comes first. ? pobe and pibf may be programmed to be the opposite logic levels shown in the diagram (positive assertion levels shown). t53 an d t54 apply to the inverted levels as well as those shown. table 86. timing requirements for phif intel mode signaling abbreviated reference parameter min max unit t55 pcsn/pods/pids pulse width (high to low) 15 ns t56 pcsn/pods/pids pulse width (low to high) 15 ns table 87. timing characteristics for phif intel mode signaling abbreviated reference parameter min max unit t53* pcsn/pods to pobe ? (high to high) 15ns t54* pcsn/pids to pibf ? (high to high) 15ns pods pids v ih v il v ih v il v ih v il t55 t56 t55 t56 t55 t56 pcsn t53 t54 16-bit read 8-bit write pbsel pobe pibf t54 v oh v ol v oh v ol v oh v ol t56 t56 t55 t53 8-bit read 16-bit write 5-4037 (f).a
data sheet dsp1627 digital signal processor march 2000 88 lucent technologies inc. 10 timing characteristics for 5 v operation (continued) figure 24. phif motorola mode signaling (read and write) timing diagram * this timing diagram for the phif port shows accesses using the pcsn signal to initiate and complete a transaction. the transac tions can also be initiated and completed with the pds signal. an input/output transaction is initiated by pcsn or pds going low, whichever co mes last. for example, the timing requirements referenced to pcsn going low, t45 and t49, should be referenced to pds going low, if pds goes low after pcsn. an input/output transaction is completed by pcsn or pds going high, whichever comes first. all requirements referenced to pcsn should be referenced to pds, if pds is the controlling signal. prwn should never be used to initiate or complete a transaction. ? pds is programmable to be active-high or active-low. it is shown active-low in figures 24 and 25. pobe and pibf may be program med to be the opposite logic levels shown in the diagram. t53 and t54 apply to the inverted levels as well as those shown. * this timing diagram for the phif port shows accesses using the pcsn signal to initiate and complete a transaction. the transac tions can also be initiated and completed with the pds signal. an input/output transaction is initiated by pcsn or pds going low, whichever co mes last. for example, the timing requirements referenced to pcsn going low, t45 and t49, should be referenced to pds going low, if pds goes low after pcsn. an input/output transaction is completed by pcsn or pds going high, whichever comes first. all requirements referenced to pcsn should be referenced to pds, if pds is the controlling signal. prwn should never be used to initiate or complete a transaction. ? pds is programmable to be active-high or active-low. it is shown active-low in figures 24 and 25. pobe and pibf may be program med to be the opposite logic levels shown in the diagram. t53 and t54 apply to the inverted levels as well as those shown. table 88. timing requirements for phif motorola mode signaling abbreviated reference parameter min max unit t41 pds ? to pcsn setup (valid to low) 0ns t42 pcsn to pds ? hold (high to invalid) 0ns t43 prwn to pcsn setup (valid to low) 4.5 ns t44 pcsn to prwn hold (high to invalid) 0 ns t45* pstat to pcsn setup (valid to low) 4.5 ns t46* pcsn to pstat hold (high to invalid) 0 ns t47* pbsel to pcsn setup (valid to low) 4.5 ns t48* pcsn to pbsel hold (high to invalid) 0 ns t51* pb write to pcsn setup (valid to high) 8 ns t52* pcsn to pb write hold (high to invalid) 4 ns table 89. timing characteristics for phif motorola mode signaling abbreviated reference parameter min max unit t49* pcsn to pb read (low to valid) 13 ns t50* pcsn to pb read (high to invalid) 3 ns 5-4038 (f).a pcsn pds prwn pbsel pstat pb[7:0] t41 t42 t43 t44 t45 t46 t47 t48 t52 t51 t50 t49 16-bit read 16-bit write t43 t44 v ih v il v ih v il v ih v il v ih v il v ih v il t154
data sheet march 2000 dsp1627 digital signal processor lucent technologies inc. 89 10 timing characteristics for 5 v operation (continued) figure 25. phif motorola mode signaling (pulse period and flags) timing diagram * an input/output transaction is initiated by pcsn or pds going low, whichever comes last. for example, t53 and t54 should be re ferenced to pds going low, if pds goes low after pcsn. an input/output transaction is completed by pcsn or pds going high, whichever comes first. all requirements referenced to pcsn should be referenced to pds, if pds is the controlling signal. prwn should never be used to initiate or complete a transaction. ? pds is programmable to be active-high or active-low. it is shown active-low in figures 24 and 25. pobe and pibf may be program med to be the opposite logic levels shown in the diagram. t53 and t54 apply to the inverted levels as well as those shown. table 90. timing characteristics for phif motorola mode signaling abbreviated reference parameter min max unit t53* pcsn/pds ? to pobe ? (high to high) 15ns t54* pcsn/pds ? to pibf ? (high to high) 15ns table 91. timing requirements for phif motorola mode signaling abbreviated reference parameter min max unit t55 pcsn/pds/prwn pulse width (high to low) 15 ns t56 pcsn/pds/prwn pulse width (low to high) 15 ns pds prwn v ih C t55 t56 t55 t56 t55 t56 pcsn t53 t54 16-bit read 8-bit write pbsel pobe pibf t54 t56 t56 t55 t53 8-bit read 16-bit write v il C v ih C v il C v ih C v il C v oh C v ol C v oh C v ol C v oh C v ol C 5-4039 (f).a
data sheet dsp1627 digital signal processor march 2000 90 lucent technologies inc. 10 timing characteristics for 5 v operation (continued) * motorola mode signal name. figure 26. phif intel or motorola mode signaling (status register read) timing diagram ? t45, t47, and t49 are referenced to the falling edge of pcsn or pods(pds), whichever occurs last. ? t46, t48, and t50 are referenced to the rising edge of pcsn or pods(pds), whichever occurs first. ? t45, t47, and t49 are referenced to the falling edge of pcsn or pods(pds), whichever occurs last. ? t46, t48, and t50 are referenced to the rising edge of pcsn or pods(pds), whichever occurs first. table 92. timing requirements for intel and motorola mode signaling (status register read) abbreviated reference parameter min max unit t45 ? pstat to pcsn setup (valid to low) 4.5 ns t46 ? pcsn to pstat hold (high to invalid) 0ns t47 ? pbsel to pcsn setup (valid to low) 4.5 ns t48 ? pcsn to pbsel hold (high to invalid) 0ns table 93. timing characteristics for intel and motorola mode signaling (status register read) abbreviated reference parameter min max unit t49 ? pcsn to pb read (low to valid) 13 ns t50 ? pcsn to pb read hold (high to invalid) 3ns pcsn pods (pds*) pids (prwn*) pbsel pstat pb[7:0] t47 t48 t45 t46 t49 t50 v ih v il v oh v ol v ih v il v ih v il v ih v il v ih v il 5-4040 (f).a t154
data sheet march 2000 dsp1627 digital signal processor lucent technologies inc. 91 10 timing characteristics for 5 v operation (continued) figure 27. phif, pibf, and pobe reset timing diagram * after reset, pobe and pibf always go to the levels shown, indicating output buffer empty and input buffer empty. the dsp progr am, however, may later invert the definition of the logic levels for pobe and pibf. t57 and t58 continue to apply. ? pobe and pibf can be programmed to be active-high or active-low. they are shown active-high. the timing characteristic for act ive-low is the same as for active-high . figure 28. phif, pibf, and pobe disable timing diagram table 94. phif timing characteristics for phif, pibf, and pobe reset abbreviated reference parameter min max unit t57 rstb disable to pobe/pibf* (high to valid) 19 ns t58 rstb enable to pobe/pibf* (low to invalid) 3 19 ns table 95. phif timing characteristics for pobe and pibf disable abbreviated reference parameter min max unit t59 cko to pobe/pibf disable (high/low to disable) 15 ns rstb v ih C t58 t57 v il C pobe v oh C v ol C pibf v oh C v ol C 5-4775 (f) cko v ih C v il C t59 t59 pobe ? v oh C v ol C pibf ? v oh C v ol C 5-4776 (f)
data sheet dsp1627 digital signal processor march 2000 92 lucent technologies inc. 10 timing characteristics for 5 v operation (continued) 10.9 serial i/o specifications * n = 16 or 8 bits. figure 29. sio passive mode input timing diagram ? device is fully static; t70 is tested at 200 ns. ? for multiprocessor mode, see note in section 10.10. table 96. timing requirements for serial inputs abbreviated reference parameter min max unit t70 clock period (high to high) ? 40 ? ns t71 clock low time (low to high) 18 ns t72 clock high time (high to low) 18 ns t73 load high setup (high to high) 6 ns t74 load low setup (low to high) 6 ns t75 load high hold (high to invalid) 0 ns t77 data setup (valid to high) 5 ns t78 data hold (high to invalid) 0 ns table 97. timing characteristics for serial outputs abbreviated reference parameter min max unit t79 ibf delay (high to high) 22 ns ibf v oh C v ol C di v ih C v il C ild v ih C v il C ick v ih C v il C bn C 1* b0 t77 t78 b0 b1 t79 t72 t71 t70 t75 t74 t75 t73 5-4777 (f)
data sheet march 2000 dsp1627 digital signal processor lucent technologies inc. 93 10 timing characteristics for 5 v operation (continued) * ild goes high during bit 6 (of 0:15), n = 8 or 16. figure 30. sio active mode input timing diagram table 98. timing requirements for serial inputs abbreviated reference parameter min max unit t77 data setup (valid to high) 5 ns t78 data hold (high to invalid) 0 ns table 99. timing characteristics for serial outputs abbreviated reference parameter min max unit t76a ild delay (high to low) 22 ns t101 ild hold (high to invalid) 4 ns t79 ibf delay (high to high) 22 ns ibf v oh C v ol C di v ih C v il C ild v oh C v ol C ick v oh C v ol C bn C 1 b0 t77 t78 b0 b1 t79 t101 t76a * 5-4778 (f)
data sheet dsp1627 digital signal processor march 2000 94 lucent technologies inc. 10 timing characteristics for 5 v operation (continued) * see sioc register, msb field to determine if b0 is the msb or lsb. see sioc register, ilen field to determine if the do word l ength is 8 bits or 16 bits. figure 31. sio passive mode output timing diagram ? device is fully static; t80 is tested at 200 ns. ? for multiprocessor mode, see note in section 10.10. table 100. timing requirements for serial inputs abbreviated reference parameter min max unit t80 clock period (high to high) ? 40 ? ns t81 clock low time (low to high) 18 ns t82 clock high time (high to low) 18 ns t83 load high setup (high to high) 6 ns t84 load low setup (low to high) 6 ns t85 load hold (high to invalid) 0 ns table 101. timing characteristics for serial outputs abbreviated reference parameter min max unit t87 data delay (high to valid) 22 ns t88 enable data delay (low to active) 22 ns t89 disable data delay (high to 3-state) 22 ns t90 data hold (high to invalid) 4 ns t92 address delay (high to valid) 22 ns t93 address hold (high to invalid) 4 ns t94 enable delay (low to active) 22 ns t95 disable delay (high to 3-state) 22 ns t96 obe delay (high to high) 22 ns doen v ih C v il C sadd v oh C v ol C old v ih C v il C ock v ih C v il C t85 t80 t81 t82 t84 t83 t85 t88 b0 b1 b7 bn C 1 t90 t90 t87 t94 ad0 ad1 ad7 t93 t93 t92 as7 t89 t95 obe v oh C v ol C do* v oh C v ol C t96 5-4796 (f)
data sheet march 2000 dsp1627 digital signal processor lucent technologies inc. 95 10 timing characteristics for 5 v operation (continued) * old goes high at the end of bit 6 of 0:15. figure 32. sio active mode output timing diagram table 102. timing characteristics for serial outputs abbreviated reference parameter min max unit t86a old delay (high to low) 22 ns t102 old hold (high to invalid) 4 ns t87 data delay (high to valid) 22 ns t88 enable data delay (low to active) 22 ns t89 disable data delay (high to 3-state) 22 ns t90 data hold (high to invalid) 4 ns t92 address delay (high to valid) 22 ns t93 address hold (high to invalid) 4 ns t94 enable delay (low to active) 22 ns t95 disable delay (high to 3-state) 22 ns t96 obe delay (high to high) 22 ns doen v ih C v il C sadd v oh C v ol C old v oh C v ol C ock v oh C v ol C t102 t86a t88 b0 b1 b7 bn C 1 t90 t90 t87 t94 ad0 ad1 ad7 t93 t93 t92 as7 t89 t95 obe v oh C v ol C do v oh C v ol C t96 * 5-4797 (f)
data sheet dsp1627 digital signal processor march 2000 96 lucent technologies inc. 10 timing characteristics for 5 v operation (continued) * see sioc register, ld field. figure 33. serial i/o active mode clock timing table 103. timing characteristics for signal generation abbreviated reference parameter min max unit t97 ick delay (high to high) 15 ns t98 ick delay (high to low) 15 ns t99 ock delay (high to high) 15 ns t100 ock delay (high to low) 15 ns t76a ild delay (high to low) 22 ns t76b ild delay (high to high) 22 ns t101 ild hold (high to invalid) 4 ns t86a old delay (high to low) 22 ns t86b old delay (high to high) 22 ns t102 old hold (high to invalid) 4 ns t103 sync delay (high to low) 22 ns t104 sync delay (high to high) 22 ns t105 sync hold (high to invalid) 4 ns ick v oh C v ol C cko v oh C v ol C t97 ock v oh C v ol C ick/ock* v oh C ild v oh C v ol C old v oh C v ol C sync v oh C v ol C t99 t98 t100 t101 t76a t101 t76b t102 t86a t102 t86b t105 t103 t105 t104 5-4798 (f)
data sheet march 2000 dsp1627 digital signal processor lucent technologies inc. 97 10 timing characteristics for 5 v operation (continued) 10.10 multiprocessor communication * negative edge initiates time slot 0. figure 34. sio multiprocessor timing diagram note: all serial i/o timing requirements and characteristics still apply, but the minimum clock period in passive multiprocessor mode, assuming 50% duty cycle, is calculated as (t77 + t116) x 2. * with capacitance load on ick, ock, do, sync, and sadd = 100 pf, add 4 ns to t116t122. table 104. timing requirements for sio multiprocessor communication abbreviated reference parameter min max unit t112 sync setup (high/low to high) 22 ns t113 sync hold (high to high/low) 0 ns t114 address setup (valid to high) 9 ns t115 address hold (high to invalid) 0 ns table 105. timing characteristics for sio multiprocessor communication abbreviated reference* parameter min max unit t116 data delay (bit 0 only) (low to valid) 22 ns t117 data disable delay (high to 3-state) 20 ns t120 doen valid delay (high to valid) 16 ns t121 address delay (bit 0 only) (low to valid) 22 ns t122 address disable delay (high to 3-state) 20 ns ock/ick b0 b15 b8 b7 b1 b0 b15 sync v ih C v il C do/d1 v oh C v ol C doen v oh C v ol C t112 t113 t112 t113 time slot 1 time slot 2 t117 t116 ad0 as7 as0 ad7 ad1 ad0 sadd t122 t121 t114 t115 t120 t120 * 5-4799 (f)
data sheet dsp1627 digital signal processor march 2000 98 lucent technologies inc. 11 timing characteristics for 3.0 v operation the following timing characteristics and requirements are preliminary information and are subject to change. timing characteristics refer to the behavior of the device under specified conditions. timing requirements refer to conditions imposed on the user for proper operation of the device. all timing data is valid for the following conditions: t a = C40 c to +85 c (see section 8.3.) v dd = 3.0 v to 3.6 v, v ss = 0 v (see section 8.3.) capacitance load on outputs (c l ) = 50 pf, except for cko, where c l = 20 pf. output characteristics can be derated as a function of load capacitance (c l ). all outputs: 0.03 ns/pf dt/dc l 0.07 ns/pf for 10 c l 100 pf at v ih for rising edge and at v il for falling edge. for example, if the actual load capacitance is 30 pf instead of 50 pf, the derating for a rising edge is (30 C 50) pf x 0.06 ns/pf = 1.2 ns less than the specified rise time or delay that includes a rise time. test conditions for inputs: n rise and fall times of 4 ns or less n timing reference levels for delays = v ih , v il test conditions for outputs (unless noted otherwise): n c load = 50 pf; except for cko, where c load = 20 pf n timing reference levels for delays = v ih , v il n 3-state delays measured to the high-impedance state of the output driver for the timing diagrams, see table 62 for input clock requirements. unless otherwise noted, cko in the timing diagrams is the free-running cko.
data sheet march 2000 dsp1627 digital signal processor lucent technologies inc. 99 11 timing characteristics for 3.0 v operation (continued) 11.1 dsp clock generation * see table 62 for input clock electrical requirements. ? free-running clock. ? wait-stated clock (see table 38). w = number of wait-states. figure 35. i/o clock timing diagram * device speeds greater than 50 mips do not support 1x operation. use the pll. ? device is fully static, t1 is tested at 100 ns for 1x input clock option, and memory hold time is tested at 0.1 s. * t = internal clock period, set by cki or by cki and the pll parameters. table 106. timing requirements for input clock abbreviated reference parameter 10 ns * min max unit t1 clock in period (high to high) 20 ? ns t2 clock in low time (low to high) 10 ns t3 clock in high time (high to low) 10 ns table 107. timing characteristics for input clock and output clock abbreviated reference parameter 10 ns unit min max t4 clock out high delay 10 ns t5 clock out low delay (high to low) 10 ns t6 clock out period (low to low) t* ns t6a clock out period with slowcki bit set in powerc register (low to low) 0.74 3.8 m s 5-4009 (f).a t4 t1 t2 1x cki* t5 cko ? t3 t6, t6a cko ? external memory cycle w = 1
data sheet dsp1627 digital signal processor march 2000 100 lucent technologies inc. 11 timing characteristics for 3.0 v operation (continued) 11.2 reset circuit the dsp1627 has a powerup reset circuit that automatically clears the jtag controller upon powerup. if the supply voltage falls below v dd min* and a reset is required, the jtag controller must be reseteven if the jtag port isnt being usedby applying six low-to-high clock edges on tck with tms held high, followed by the usual rstb and cki reset sequence. figure 60 shows two separate events: an initial powerup and a powerup following a drop in the power supply voltage. * see table 60, recommended operating condiitons. notes: see table 62 for cki electrical requirements and table 151 for tck timing requirements. when both int0 and rstb are asserted, all output and bidirectional pins (except tdo, which 3-states by jtag control) are put in a 3-state condition. with rstb asserted and int0 not asserted, erom, eramhi, eramlo, io, dsel, and rwn outputs remain high, and cko remai ns a free-running clock. tms and tdi signals have internal pull-up devices. figure 36. powerup reset and chip reset timing diagram * with external components as specified in table 62. ?t tck = t12 = tck period. see table 151 for tck timing requirements. table 108. timing requirements for powerup reset and chip reset abbreviated reference parameter min max unit t8 reset pulse (low to high) 6t ns t9 v dd ramp 10 ms t146 v dd min to rstb low cmos crystal* small-signal 2t 20 20 ns ms m s t151 tms high 6 * t tck ? ns t152 jtag reset to cmos rstb low crystal* small-signal 2t 20 ms C 6 * t tck if 6 * t tck < 20 ms 0 if 6 * t tck 3 20 ms 20 s C 6 * t tck if 6 * t tck < 20 s 0 if 6 * t tck 3 20 s ns t153 rstb (low to high) 54 ns 5-2253 (f).a t10 t11 t10 t11 t9 t146 t8 t9 t151 t152 t8 v dd ramp cki tck tms rstb pins v oh v ol v ih v il v ih 0.4 v v dd min v dd min 0.4 v t153 t153
data sheet march 2000 dsp1627 digital signal processor lucent technologies inc. 101 11 timing characteristics for 3.0 v operation (continued) note: the device needs to be clocked for at least six cki cycles during reset after powerup. otherwise, high cur- rents may flow. 11.3 reset synchronization * see table 62 for input clock electrical requirements. note: cko 1 and cko 2 are two possible cko states before reset. cko is free-running. figure 37. reset synchronization timing table 109. timing characteristics for powerup reset and chip reset abbreviated reference parameter min max unit t10 rstb disable time (low to 3-state) 100 ns t11 rstb enable time (high to valid) 100 ns table 110. timing requirements for reset synchronization timing abbreviated reference parameter min max unit t126 reset setup (high to high) 3 t/2 C 5 ns 5-4011 (f).a cki * v ih v il t126 t5 + 2 x t6 rstb v ih v il v ih v il cko v ih v il cko
data sheet dsp1627 digital signal processor march 2000 102 lucent technologies inc. 11 timing characteristics for 3.0 v operation (continued) 11.4 jtag i/o specifications figure 38. jtag timing diagram table 111. timing requirements for jtag input/output abbreviated reference parameter min max unit t12 tck period (high to high) 50 ns t13 tck high time (high to low) 22.5 ns t14 tck low time (low to high) 22.5 ns t15 tms setup time (valid to high) 7.5 ns t16 tms hold time (high to invalid) 2 ns t17 tdi setup time (valid to high) 7.5 ns t18 tdi hold time (high to invalid) 2 ns table 112. timing characteristics for jtag input/output abbreviated reference parameter min max unit t19 tdo delay (low to valid) 19 ns t20 tdo hold (low to invalid) 0 ns t12 t14 t13 t15 t16 t17 t18 t19 t20 tck tms tdi tdo v ih v il v ih v il v ih v il v oh v ol t155 5-4017 (f) t156
data sheet march 2000 dsp1627 digital signal processor lucent technologies inc. 103 11 timing characteristics for 3.0 v operation (continued) 11.5 interrupt * cko is free-running. ? iack assertion is guaranteed to be enclosed by vec[3:0] assertion. figure 39. interrupt timing diagram note: interrupt is asserted during an interruptible instruction and no other pending interrupts. note: interrupt is asserted during an interruptible instruction and no other pending interrupts. table 113. timing requirements for interrupt abbreviated reference parameter min max unit t21 interrupt setup (high to low) 19 ns t22 int assertion time (high to low) 2t ns table 114. timing characteristics for interrupt abbreviated reference parameter min max unit t23 iack assertion time (low to high) t/2 + 10 ns t24 vec assertion time (low to high) 12.5 ns t25 iack invalid time (low to low) 10 ns t26 vec invalid time (low to low) 12.5 ns 5-4018 (f) cko * int[1:0] t21 v oh v ol v ih v il t22 iack ? v oh v ol vec[3:0] v oh v ol t23 t24 t25 t26
data sheet dsp1627 digital signal processor march 2000 104 lucent technologies inc. 11 timing characteristics for 3.0 v operation (continued) 11.6 bit input/output (bio) figure 40. write outputs followed by read inputs (cbit = immediate; a1 = sbit) figure 41. write outputs and test inputs (cbit = immediate) table 115. timing requirements for bio input read abbreviated reference parameter min max unit t27 iobit input setup time (valid to high) 15 ns t28 iobit input hold time (high to invalid) 0 ns table 116. timing characteristics for bio output abbreviated reference parameter min max unit t29 iobit output valid time (low to valid) 9 ns t144 iobit output hold time (low to invalid) 1 ns table 117. timing requirements for bio input test abbreviated reference parameter min max unit t141 iobit input setup time (valid to low) 15 ns t142 iobit input hold time (low to invalid) 0 ns 5-4019 (f).a cko iobit (input) t28 t27 valid output v i h v i l v o h v o l v o h v o l data input t29 t144 iobit (output) 5-4019 (f).b cko iobit (input) t142 t141 valid output v oh C v o lC test input t29 t144 iobit (output) v oh C v o lC v ih C v i lC
data sheet march 2000 dsp1627 digital signal processor lucent technologies inc. 105 11 timing characteristics for 3.0 v operation (continued) 11.7 external memory interface the following timing diagrams, characteristics, and requirements do not apply to interactions with delayed external memory enables unless so stated. see the dsp1611/17/18/27 digital signal processor information manual for a detailed description of the external memory interface including other functional diagrams. * w = number of wait-states. figure 42. enable transition timing table 118. timing characteristics for external memory enables (erom, eramhi, io, eramlo) abbreviated reference parameter min max unit t33 cko to enable active (low to low) 0 5 ns t34 cko to enable inactive (low to high) C1 4.5 ns table 119. timing characteristics for delayed external memory enables (ioc = 0x000f) abbreviated reference parameter min max unit t33 cko to delayed enable active (low to low) t/2 C 2 t/2 + 7 ns cko enable t34 t33 w * = 0 v oh v ol v oh v ol 5-4020 (f).b
data sheet dsp1627 digital signal processor march 2000 106 lucent technologies inc. 11 timing characteristics for 3.0 v operation (continued) * w = number of wait-states. figure 43. external memory data read timing diagram table 120. timing characteristics for external memory access abbreviated reference parameter min max unit t127 enable width (low to high) t(1 + w) C 1.5 ns t128 address valid (enable low to valid) 2 ns table 121. timing requirements for external memory read (erom, eramhi, io, eramlo) abbreviated reference parameter 10 ns unit min max t129 read data setup (valid to enable high) 13 ns t130 read data hold (enable high to hold) 0 ns t150 external memory access time (valid to valid) t(1 + w) C 13 ns v ih v il db cko ab v oh v ol t128 read address enable v oh v ol v oh v ol (mwait = 0 x 2222) w* = 2 t127 t129 t130 read data t150 5-4021 (f).a
data sheet march 2000 dsp1627 digital signal processor lucent technologies inc. 107 11 timing characteristics for 3.0 v operation (continued) * w = number of wait-states. figure 44. external memory data write timing diagram table 122. timing characteristics for external memory data write (all enables) abbreviated reference parameter 10 ns unit min max t131 write overlap (enable low to 3-state) 0 ns t132 rwn advance (rwn high to enable high) 0 ns t133 rwn delay (enable low to rwn low) 0 ns t134 write data setup (data valid to rwn high) t(1 + w)/2 C 3 ns t135 rwn width (low to high) t(1 + w) C 4 ns t136 write address setup (address valid to rwn low) 0 ns eramlo erom cko ab rwn db write address read address v oh v ol v oh v ol v oh v ol v oh v ol v oh v ol write data read w* = 1 t131 t132 t134 t133 t135 t136 (mwait = 0x1002) w* = 2 v oh v ol 5-4022 (f).a
data sheet dsp1627 digital signal processor march 2000 108 lucent technologies inc. 11 timing characteristics for 3.0 v operation (continued) * w = number of wait-states. figure 45. write cycle followed by read cycle table 123. timing characteristics for write cycle followed by read cycle abbreviated reference parameter min max unit t131 write overlap (enable low to 3-state) 0 ns t137 write data 3-state (rwn high to 3-state) 2 ns t138 write data hold (rwn high to data hold) 0 ns t139 write address hold (rwn high to address hold) 0 ns eramlo cko ab rwn write address read address v oh v ol v oh v ol v oh v ol v oh v ol w* = 1 t137 (mwait = 0x1002) w* = 2 erom v oh v ol db write read v oh v ol t138 t139 t131 5-4023 (f).a
data sheet march 2000 dsp1627 digital signal processor lucent technologies inc. 109 11 timing characteristics for 3.0 v operation (continued) 11.8 phif specifications for the phif, "read" means read by the external user (output by the dsp); "write" is similarly defined. the 8-bit reads/ writes are identical to one-half of a 16-bit access. figure 46. phif intel mode signaling (read and write) timing diagram * this timing diagram for the phif port shows accesses using the pcsn signal to initiate and complete a transaction. the transac tions can also be initiated and completed with the pids and pods signals. an output transaction (read) is initiated by pcsn or pods going low, wh ichever comes last. for example, the timing requirements referenced to pcsn going low, t45 and t49, should be referenced to pods going low, i f pods goes low after pcsn. an output transaction is completed by pcsn or pods going high, whichever comes first. an input transaction is i nitiated by pcsn or pids going low, whichever comes last. an input transaction is completed by pcsn or pids going high, whichever comes first. a ll requirements referenced to pcsn apply to pids or pods, if pids or pods is the controlling signal. * this timing diagram for the phif port shows accesses using the pcsn signal to initiate and complete a transaction. the transac tions can also be initiated and completed with the pids and pods signals. an output transaction (read) is initiated by pcsn or pods going low, wh ichever comes last. for example, the timing requirements referenced to pcsn going low, t45 and t49, should be referenced to pods going low, i f pods goes low after pcsn. an output transaction is completed by pcsn or pods going high, whichever comes first. an input transaction is i nitiated by pcsn or pids going low, whichever comes last. an input transaction is completed by pcsn or pids going high, whichever comes first. a ll requirements referenced to pcsn apply to pids or pods, if pids or pods is the controlling signal. table 124. timing requirements for phif intel mode signaling abbreviated reference parameter min max unit t41 pods to pcsn setup (low to low) 0 ns t42 pcsn to pods hold (high to high) 0 ns t43 pids to pcsn setup (low to low) 0 ns t44 pcsn to pids hold (high to high) 0 ns t45* pstat to pcsn setup (valid to low) 6 ns t46* pcsn to pstat hold (high to invalid) 0 ns t47* pbsel to pcsn setup (valid to low) 6 ns t48* pcsn to pbsel hold (high to invalid) 0 ns t51* pb write to pcsn setup (valid to high) 10 ns t52* pcsn to pb write hold (high to invalid) 5 ns table 125. timing characteristics for phif intel mode signaling abbreviated reference parameter min max unit t49* pcsn to pb read (low to valid) 17 ns t50* pcsn to pb read hold (high to invalid) 3 ns 5-4036 (f) pcsn t41 t42 t43 t45 t46 t49 t50 16-bit read 16-bit write pods pids pbsel pstat pb[7:0] t47 t51 t52 t48 t44 t154 v ihC v ilC v ihC v ilC v ihC v ilC v ihC v ilC v ihC v ilC v ihC v ilC
data sheet dsp1627 digital signal processor march 2000 110 lucent technologies inc. 11 timing characteristics for 3.0 v operation (continued) figure 47. phif intel mode signaling (pulse period and flags) timing diagram * t53 should be referenced to the rising edge of pcsn or pods, whichever comes first. t54 should be referenced to the rising edge of pcsn or pids, whichever comes first. ? pobe and pibf may be programmed to be the opposite logic levels shown in the diagram (positive assertion levels shown). t53 an d t54 apply to the inverted levels as well as those shown. table 126. timing requirements for phif intel mode signaling abbreviated reference parameter min max unit t55 pcsn/pods/pids pulse width (high to low) 20.5 ns t56 pcsn/pods/pids pulse width (low to high) 20.5 ns table 127. timing characteristics for phif intel mode signaling abbreviated reference parameter min max unit t53* pcsn/pods to pobe ? (high to high) 20ns t54* pcsn/pids to pibf ? (high to high) 20ns pods pids v ih v il v ih v il v ih v il t55 t56 t55 t56 t55 t56 pcsn t53 t54 16-bit read 8-bit write pbsel pobe pibf t54 v oh v ol v oh v ol v oh v ol t56 t56 t55 t53 8-bit read 16-bit write 5-4037 (f).a
data sheet march 2000 dsp1627 digital signal processor lucent technologies inc. 111 11 timing characteristics for 3.0 v operation (continued) figure 48. phif motorola mode signaling (read and write) timing diagram * this timing diagram for the phif port shows accesses using the pcsn signal to initiate and complete a transaction. the transac tions can also be initiated and completed with the pds signal. an input/output transaction is initiated by pcsn or pds going low, whichev er comes last. for example, the timing requirements referenced to pcsn going low, t45 and t49, should be referenced to pds going low, if pds g oes low after pcsn. an input/output transaction is completed by pcsn or pds going high, whichever comes first. all requirements referen ced to pcsn should be referenced to pds, if pds is the controlling signal. prwn should never be used to initiate or complete a transac tion. ? pds is programmable to be active-high or active-low. it is shown active-low in figures 72 and 73. pobe and pibf may be program med to be the opposite logic levels shown in the diagram. t53 and t54 apply to the inverted levels as well as those shown. * this timing diagram for the phif port shows accesses using the pcsn signal to initiate and complete a transaction. the transac tions can also be initiated and completed with the pds signal. an input/output transaction is initiated by pcsn or pds going low, whichev er comes last. for example, the timing requirements referenced to pcsn going low, t45 and t49, should be referenced to pds going low, if pds g oes low after pcsn. an input/output transaction is completed by pcsn or pds going high, whichever comes first. all requirements referen ced to pcsn should be referenced to pds, if pds is the controlling signal. prwn should never be used to initiate or complete a transac tion. table 128. timing requirements for phif motorola mode signaling abbreviated reference parameter min max unit t41 pds ? to pcsn setup (valid to low) 0ns t42 pcsn to pds ? hold (high to invalid) 0ns t43 prwn to pcsn setup (valid to low) 6 ns t44 pcsn to prwn hold (high to invalid) 0 ns t45* pstat to pcsn setup (valid to low) 6 ns t46* pcsn to pstat hold (high to invalid) 0 ns t47* pbsel to pcsn setup (valid to low) 6 ns t48* pcsn to pbsel hold (high to invalid) 0 ns t51* pb write to pcsn setup (valid to high) 10 ns t52* pcsn to pb write hold (high to invalid) 5 ns table 129. timing characteristics for phif motorola mode signaling abbreviated reference parameter min max unit t49* pcsn to pb read (low to valid) 17 ns t50* pcsn to pb read (high to invalid) 3 ns pcsn pds prwn pbsel pstat pb[7:0] t41 t42 t43 t44 t45 t46 t47 t48 t52 t51 t50 t49 16-bit read 16-bit write t43 t44 v ih v il v ih v il v ih v il v ih v il v ih v il 5-4038 (f).a t154
data sheet dsp1627 digital signal processor march 2000 112 lucent technologies inc. 11 timing characteristics for 3.0 v operation (continued) figure 49. phif motorola mode signaling (pulse period and flags) timing diagram * an input/output transaction is initiated by pcsn or pds going low, whichever comes last. for example, t53 and t54 should be r eferenced to pds going low, if pds goes low after pcsn. an input/output transaction is completed by pcsn or pds going high, whichever comes first. all requirements referenced to pcsn should be referenced to pds, if pds is the controlling signal. prwn should never be used to initiate or complete a transaction. ? pds is programmable to be active-high or active-low. it is shown active-low in figures 48 and 49. pobe and pibf may be program med to be the opposite logic levels shown in the diagram. t53 and t54 apply to the inverted levels as well as those shown. table 130. timing characteristics for phif motorola mode signaling abbreviated reference parameter min max unit t53* pcsn/pds ? to pobe ? (high to high) 20ns t54* pcsn/pds ? to pibf ? (high to high) 20ns table 131. timing requirements for phif motorola mode signaling abbreviated reference parameter min max unit t55 pcsn/pds/prwn pulse width (high to low) 20 ns t56 pcsn/pds/prwn pulse width (low to high) 20 ns pds prwn v ih C t55 t56 t55 t56 t55 t56 pcsn t53 t54 16-bit read 8-bit write pbsel pobe pibf t54 t56 t56 t55 t53 8-bit read 16-bit write v il C v ih C v il C v ih C v il C v oh C v ol C v oh C v ol C v oh C v ol C 5-4039 (f).a
data sheet march 2000 dsp1627 digital signal processor lucent technologies inc. 113 11 timing characteristics for 3.0 v operation (continued) * motorola mode signal name. figure 50. phif intel or motorola mode signaling (status register read) timing diagram ? t45, t47, and t49 are referenced to the falling edge of pcsn or pods(pds), whichever occurs last. ? t46, t48, and t50 are referenced to the rising edge of pcsn or pods(pds), whichever occurs first. ? t45, t47, and t49 are referenced to the falling edge of pcsn or pods(pds), whichever occurs last. ? t46, t48, and t50 are referenced to the rising edge of pcsn or pods(pds), whichever occurs first. table 132. timing requirements for intel and motorola mode signaling (status register read) abbreviated reference parameter min max unit t45 ? pstat to pcsn setup (valid to low) 6 ns t46 ? pcsn to pstat hold (high to invalid) 0 ns t47 ? pbsel to pcsn setup (valid to low) 6 ns t48 ? pcsn to pbsel hold (high to invalid) 0 ns table 133. timing characteristics for intel and motorola mode signaling (status register read) abbreviated reference parameter min max unit t49 ? pcsn to pb read (low to valid) 17 ns t50 ? pcsn to pb read hold (high to invalid) 3 ns pcsn pods (pds*) pids (prwn*) pbsel pstat pb[7:0] t47 t48 t45 t46 t49 t50 v ih v il v oh v ol v ih v il v ih v il v ih v il v ih v il 5-4040 (f).a t154
data sheet dsp1627 digital signal processor march 2000 114 lucent technologies inc. 11 timing characteristics for 3.0 v operation (continued) figure 51. phif, pibf, and pobe reset timing diagram ? pobe and pibf can be programed to be active-high or active-low. they are shown active-high. the timing characteristic for acti ve-low is the same as for active-high. figure 52. phif, pibf, and pobe disable timing diagram table 134. phif timing characteristics for phif, pibf, and pobe reset abbreviated reference parameter min max unit t57 rstb disable to pobe/pibf * (high to valid) * after reset, pobe and pibf always go to the levels shown, indicating output buffer empty and input buffer empty. the dsp progr am, however, may later invert the definition of the logic levels for pobe and pibf. t57 and t58 continue to apply. 25 ns t58 rstb enable to pobe/pibf* (low to invalid) 325ns table 135. phif timing characteristics for pobe and pibf disable abbreviated reference parameter min max unit t59 cko to pobe/pibf * disable (high/low to disable) * pobe and pibf can be programmed to be active-high or active-low. they are shown active-high. the timing characteristic for act ive-low is the same as for active-high. 20 ns rstb v ih C t58 t57 v il C pobe v oh C v ol C pibf v oh C v ol C 5-4775 (f) cko v ih C v il C t59 t59 pobe ? v oh C v ol C pibf ? v oh C v ol C 5-4776 (f)
data sheet march 2000 dsp1627 digital signal processor lucent technologies inc. 115 11 timing characteristics for 3.0 v operation (continued) 11.9 serial i/o specifications * n = 16 or 8 bits. figure 53. sio passive mode input timing diagram ? device is fully static; t70 is tested at 200 ns. ? for multiprocessor mode, see note in section 12.10. table 136. timing requirements for serial inputs abbreviated reference parameter min max unit t70 clock period (high to high) ? 40 ? ns t71 clock low time (low to high) 18 ns t72 clock high time (high to low) 18 ns t73 load high setup (high to high) 8 ns t74 load low setup (low to high) 8 ns t75 load high hold (high to invalid) 0 ns t77 data setup (valid to high) 7 ns t78 data hold (high to invalid) 0 ns table 137. timing characteristics for serial outputs abbreviated reference parameter min max unit t79 ibf delay (high to high) 35 ns ibf v oh C v ol C di v ih C v il C ild v ih C v il C ick v ih C v il C bn C 1* b0 t77 t78 b0 b1 t79 t72 t71 t70 t75 t74 t75 t73 5-4777 (f)
data sheet dsp1627 digital signal processor march 2000 116 lucent technologies inc. 11 timing characteristics for 3.0 v operation (continued) * ild goes high during bit 6 (of 0:15), n = 8 or 16. figure 54. sio active mode input timing diagram table 138. timing requirements for serial inputs abbreviated reference parameter min max unit t77 data setup (valid to high) 7 ns t78 data hold (high to invalid) 0 ns table 139. timing characteristics for serial outputs abbreviated reference parameter min max unit t76a ild delay (high to low) 35 ns t101 ild hold (high to invalid) 5 ns t79 ibf delay (high to high) 35 ns ibf v oh C v ol C di v ih C v il C ild v oh C v ol C ick v oh C v ol C bn C 1 b0 t77 t78 b0 b1 t79 t101 t76a * 5-4778 (f)
data sheet march 2000 dsp1627 digital signal processor lucent technologies inc. 117 11 timing characteristics for 3.0 v operation (continued) * see sioc register, msb field, to determine if b0 is the msb or lsb. see sioc register, ilen field, to determine if the do word length is 8 bits or 16 bits. figure 55. sio passive mode output timing diagram ? device is fully static; t80 is tested at 200 ns. ? for multiprocessor mode, see note in section 12.10. table 140. timing requirements for serial inputs abbreviated reference parameter min max unit t80 clock period (high to high) ? 40 ? ns t81 clock low time (low to high) 18 ns t82 clock high time (high to low) 18 ns t83 load high setup (high to high) 8 ns t84 load low setup (low to high) 8 ns t85 load hold (high to invalid) 0 ns table 141. timing characteristics for serial outputs abbreviated reference parameter min max unit t87 data delay (high to valid) 35 ns t88 enable data delay (low to active) 35 ns t89 disable data delay (high to 3-state) 35 ns t90 data hold (high to invalid) 5 ns t92 address delay (high to valid) 35 ns t93 address hold (high to invalid) 5 ns t94 enable delay (low to active) 35 ns t95 disable delay (high to 3-state) 35 ns t96 obe delay (high to high) 35 ns doen v ih C v il C sadd v oh C v ol C old v ih C v il C ock v ih C v il C t85 t80 t81 t82 t84 t83 t85 t88 b0 b1 b7 bn C 1 t90 t90 t87 t94 ad0 ad1 ad7 t93 t93 t92 as7 t89 t95 obe v oh C v ol C do* v oh C v ol C t96 5-4796 (f)
data sheet dsp1627 digital signal processor march 2000 118 lucent technologies inc. 11 timing characteristics for 3.0 v operation (continued) * old goes high at the end of bit 6 of 0:15. figure 56. sio active mode output timing diagram table 142. timing characteristics for serial output abbreviated reference parameter min max unit t86a old delay (high to low) 35 ns t102 old hold (high to invalid) 5 ns t87 data delay (high to valid) 35 ns t88 enable data delay (low to active) 35 ns t89 disable data delay (high to 3-state) 35 ns t90 data hold (high to invalid) 5 ns t92 address delay (high to valid) 35 ns t93 address hold (high to invalid) 5 ns t94 enable delay (low to active) 35 ns t95 disable delay (high to 3-state) 35 ns t96 obe delay (high to high) 35 ns doen v ih C v il C sadd v oh C v ol C old v oh C v ol C ock v oh C v ol C t102 t86a t88 b0 b1 b7 bn C 1 t90 t90 t87 t94 ad0 ad1 ad7 t93 t93 t92 as7 t89 t95 obe v oh C v ol C do v oh C v ol C t96 * 5-4797 (f)
data sheet march 2000 dsp1627 digital signal processor lucent technologies inc. 119 11 timing characteristics for 3.0 v operation (continued) * see sioc register, ld field. figure 57. serial i/o active mode clock timing table 143. timing characteristics for signal generation abbreviated reference parameter min max unit t97 ick delay (high to high) 18 ns t98 ick delay (high to low) 18 ns t99 ock delay (high to high) 18 ns t100 ock delay (high to low) 18 ns t76a ild delay (high to low) 35 ns t76b ild delay (high to high) 35 ns t101 ild hold (high to invalid) 5 ns t86a old delay (high to low) 35 ns t86b old delay (high to high) 35 ns t102 old hold (high to invalid) 5 ns t103 sync delay (high to low) 35 ns t104 sync delay (high to high) 35 ns t105 sync hold (high to invalid) 5 ns ick v oh C v ol C cko v oh C v ol C t97 ock v oh C v ol C ick/ock* v oh C ild v oh C v ol C old v oh C v ol C sync v oh C v ol C t99 t98 t100 t101 t76a t101 t76b t102 t86a t102 t86b t105 t103 t105 t104 5-4798 (f)
data sheet dsp1627 digital signal processor march 2000 120 lucent technologies inc. 11 timing characteristics for 3.0 v operation (continued) 11.10 multiprocessor communication * negative edge initiates time slot 0. figure 58. sio multiprocessor timing diagram note: all serial i/o timing requirements and characteristics still apply, but the minimum clock period in passive multiprocessor mode, assuming 50% duty cycle, is calculated as (t77 + t116) x 2. * with capacitance load on ick, ock, do, sync, and sadd = 100 pf, add 4 ns to t116t122. table 144. timing requirements for sio multiprocessor communication abbreviated reference parameter min max unit t112 sync setup (high/low to high) 35 ns t113 sync hold (high to high/low) 0 ns t114 address setup (valid to high) 12 ns t115 address hold (high to invalid) 0 ns table 145. timing characteristics for sio multiprocessor communication abbreviated reference * parameter min max unit t116 data delay (bit 0 only) (low to valid) 35 ns t117 data disable delay (high to 3-state) 30 ns t120 doen valid delay (high to valid) 25 ns t121 address delay (bit 0 only) (low to valid) 35 ns t122 address disable delay (high to 3-state) 30 ns ock/ick b0 b15 b8 b7 b1 b0 b15 sync v ih C v il C do/d1 v oh C v ol C doen v oh C v ol C t112 t113 t112 t113 time slot 1 time slot 2 t117 t116 ad0 as7 as0 ad7 ad1 ad0 sadd t122 t121 t114 t115 t120 t120 * 5-4799 (f)
data sheet march 2000 dsp1627 digital signal processor lucent technologies inc. 121 12 timing characteristics for 2.7 v operation the following timing characteristics and requirements are preliminary information and are subject to change. timing characteristics refer to the behavior of the device under specified conditions. timing requirements refer to conditions imposed on the user for proper operation of the device. all timing data is valid for the following conditions: t a = C40 c to +85 c (see section 8.3.) v dd = 3 v 10%, v ss = 0 v (see section 8.3.) capacitance load on outputs (c l ) = 50 pf, except for cko, where c l = 20 pf. output characteristics can be derated as a function of load capacitance (c l ). all outputs: 0.03 ns/pf dt/dc l 0.07 ns/pf for 10 c l 100 pf at v ih for rising edge and at v il for falling edge. for example, if the actual load capacitance is 30 pf instead of 50 pf, the derating for a rising edge is (30 C 50) pf x 0.06 ns/pf = 1.2 ns less than the specified rise time or delay that includes a rise time. test conditions for inputs: n rise and fall times of 4 ns or less n timing reference levels for delays = v ih , v il test conditions for outputs (unless noted otherwise): n c load = 50 pf; except for cko, where c load = 20 pf n timing reference levels for delays = v ih , v il n 3-state delays measured to the high-impedance state of the output driver for the timing diagrams, see table 62 for input clock requirements. unless otherwise noted, cko in the timing diagrams is the free-running cko.
data sheet dsp1627 digital signal processor march 2000 122 lucent technologies inc. 12 timing characteristics for 2.7 v operation (continued) 12.1 dsp clock generation * see table 62 for input clock electrical requirements. ? free-running clock. ? wait-stated clock (see table 38). w = number of wait-states. figure 59. i/o clock timing diagram * device speeds greater than 50 mips do not support 1 x operation. use the pll. ? device is fully static, t1 is tested at 100 ns for 1x input clock option, and memory hold time is tested at 0.1 s. * t = internal clock period, set by cki or by cki and the pll parameters. table 146. timing requirements for input clock abbreviated reference parameter 20 ns and 12.5 ns * min max unit t1 clock in period (high to high) 20 ? ns t2 clock in low time (low to high) 10 ns t3 clock in high time (high to low) 10 ns table 147. timing characteristics for input clock and output clock abbreviated reference parameter 20 ns 12.5 ns unit min max min max t4 clock out high delay 14 10 ns t5 clock out low delay (high to low) 14 10 ns t6 clock out period (low to low) t* t* ns t6a clock out period with slowcki bit set in powerc register (low to low) 0.74 3.8 0.74 3.8 m s 5-4009 (f).a t4 t1 t2 1x cki* t5 cko ? t3 t6, t6a cko ? external memory cycle w = 1
data sheet march 2000 dsp1627 digital signal processor lucent technologies inc. 123 12 timing characteristics for 2.7 v operation (continued) 12.2 reset circuit the dsp1627 has a powerup reset circuit that automatically clears the jtag controller upon powerup. if the supply voltage falls below v dd min* and a reset is required, the jtag controller must be reseteven if the jtag port isnt being usedby applying six low-to-high clock edges on tck with tms held high, followed by the usual rstb and cki reset sequence. figure 60 shows two separate events: an initial powerup and a powerup following a drop in the power supply voltage. * see table 60, recommended operating condiitons. notes: see table 62 for cki electrical requirements and table 151 for tck timing requirements. when both int0 and rstb are asserted, all output and bidirectional pins (except tdo, which 3-states by jtag control) are put in a 3-state condition. with rstb asserted and int0 not asserted, erom, eramhi, eramlo, io, dsel, and rwn outputs remain high, and cko remai ns a free-running clock. tms and tdi signals have internal pull-up devices. figure 60. powerup reset and chip reset timing diagram * with external components as specified in table 62. ?t tck = t12 = tck period. see table 151 for tck timing requirements. table 148. timing requirements for powerup reset and chip reset abbreviated reference parameter min max unit t8 reset pulse (low to high) 6t ns t9 v dd ramp 10 ms t146 v dd min to rstb low cmos crystal* small-signal 2t 20 20 ns ms m s t151 tms high 6 * t tck ? ns t152 jtag reset to cmos rstb low crystal* small-signal 2t 20 ms C 6 * t tck if 6 * t tck < 20 ms 0 if 6 * t tck 3 20 ms 20 s C 6 * t tck if 6 * t tck < 20 s 0 if 6 * t tck 3 20 s ns t153 rstb (low to high) 54 ns 5-2253 (f).a t10 t11 t10 t11 t9 t146 t8 t9 t151 t152 t8 v dd ramp cki tck tms rstb pins v oh v ol v ih v il v ih 0.4 v v dd min v dd min 0.4 v t153 t153
data sheet dsp1627 digital signal processor march 2000 124 lucent technologies inc. 12 timing characteristics for 2.7 v operation (continued) note: the device needs to be clocked for at least six cki cycles during reset after powerup. otherwise, high cur- rents may flow. 12.3 reset synchronization * see table 62 for input clock electrical requirements. note: cko 1 and cko 2 are two possible cko states before reset. cko is free-running. figure 61. reset synchronization timing table 149. timing characteristics for powerup reset and chip reset abbreviated reference parameter min max unit t10 rstb disable time (low to 3-state) 100 ns t11 rstb enable time (high to valid) 100 ns table 150. timing requirements for reset synchronization timing abbreviated reference parameter min max unit t126 reset setup (high to high) 3 t/2 C 5 ns 5-4011 (f). a cki * v ih v il t126 t5 + 2 x t6 rstb v ih v il v ih v il cko v ih v il cko
data sheet march 2000 dsp1627 digital signal processor lucent technologies inc. 125 12 timing characteristics for 2.7 v operation (continued) 12.4 jtag i/o specifications figure 62. jtag timing diagram table 151. timing requirements for jtag input/output abbreviated reference parameter min max unit t12 tck period (high to high) 50 ns t13 tck high time (high to low) 22.5 ns t14 tck low time (low to high) 22.5 ns t15 tms setup time (valid to high) 7.5 ns t16 tms hold time (high to invalid) 2 ns t17 tdi setup time (valid to high) 7.5 ns t18 tdi hold time (high to invalid) 2 ns table 152. timing characteristics for jtag input/output abbreviated reference parameter min max unit t19 tdo delay (low to valid) 19 ns t20 tdo hold (low to invalid) 0 ns t12 t14 t13 t15 t16 t17 t18 t19 t20 tck tms tdi tdo v ih v il v ih v il v ih v il v oh v ol t155 t156 5-4017 (f)
data sheet dsp1627 digital signal processor march 2000 126 lucent technologies inc. 12 timing characteristics for 2.7 v operation (continued) 12.5 interrupt * cko is free-running. ? iack assertion is guaranteed to be enclosed by vec[3:0] assertion. figure 63. interrupt timing diagram note: interrupt is asserted during an interruptible instruction and no other pending interrupts. note: interrupt is asserted during an interruptible instruction and no other pending interrupts. table 153. timing requirements for interrupt abbreviated reference parameter min max unit t21 interrupt setup (high to low) 19 ns t22 int assertion time (high to low) 2t ns table 154. timing characteristics for interrupt abbreviated reference parameter min max unit t23 iack assertion time (low to high) t/2 + 10 ns t24 vec assertion time (low to high) 12.5 ns t25 iack invalid time (low to low) 10 ns t26 vec invalid time (low to low) 12.5 ns 5-4018 (f) cko * int[1:0] t21 v oh v ol v ih v il t22 iack ? v oh v ol vec[3:0] v oh v ol t23 t24 t25 t26
data sheet march 2000 dsp1627 digital signal processor lucent technologies inc. 127 12 timing characteristics for 2.7 v operation (continued) 12.6 bit input/output (bio) figure 64. write outputs followed by read inputs (cbit = immediate; a1 = sbit) figure 65. write outputs and test inputs (cbit = immediate) table 155. timing requirements for bio input read abbreviated reference parameter min max unit t27 iobit input setup time (valid to high) 15 ns t28 iobit input hold time (high to invalid) 0 ns table 156. timing characteristics for bio output abbreviated reference parameter min max unit t29 iobit output valid time (low to valid) 9 ns t144 iobit output hold time (low to invalid) 1 ns table 157. timing requirements for bio input test abbreviated reference parameter min max unit t141 iobit input setup time (valid to low) 15 ns t142 iobit input hold time (low to invalid) 0 ns cko iobit (input) t28 t27 valid output v i h v i l v o h v o l v o h v o l data input t29 t144 iobit (output) 5-4019 (f).a cko iobit (input) t142 t141 valid output v oh C v o lC test input t29 t144 iobit (output) v oh C v o lC v ih C v i lC 5-4019 (f).b
data sheet dsp1627 digital signal processor march 2000 128 lucent technologies inc. 12 timing characteristics for 2.7 v operation (continued) 12.7 external memory interface the following timing diagrams, characteristics, and requirements do not apply to interactions with delayed external memory enables unless so stated. see the dsp1611/17/18/27 digital signal processor information manual for a detailed description of the external memory interface including other functional diagrams. * w = number of wait-states. figure 66. enable transition timing table 158. timing characteristics for external memory enables (erom, eramhi, io, eramlo) abbreviated reference parameter min max unit t33 cko to enable active (low to low) 0 5 ns t34 cko to enable inactive (low to high) C1 4.5 ns table 159. timing characteristics for delayed external memory enables (ioc = 0x000f) abbreviated reference parameter min max unit t33 cko to delayed enable active (low to low) t/2 C 2 t/2 + 7 ns cko enable t34 t33 w * = 0 v oh v ol v oh v ol 5-4020 (f).b
data sheet march 2000 dsp1627 digital signal processor lucent technologies inc. 129 12 timing characteristics for 2.7 v operation (continued) * w = number of wait-states. figure 67. external memory data read timing diagram table 160. timing characteristics for external memory access abbreviated reference parameter min max unit t127 enable width (low to high) t(1 + w) C 1.5 ns t128 address valid (enable low to valid) 2 ns table 161. timing requirements for external memory read (erom, eramhi, io, eramlo) abbreviated reference parameter 20 ns 12.5 ns unit min max min max t129 read data setup (valid to enable high) 15 13 ns t130 read data hold (enable high to hold) 0 0 ns t150 external memory access time (valid to valid) t(1 + w) C 15 t(1 + w) C 14 ns v ih v il db cko ab v oh v ol t128 read address enable v oh v ol v oh v ol (mwait = 0 x 2222) w* = 2 t127 t129 t130 read data t150 5-4021 (f).a
data sheet dsp1627 digital signal processor march 2000 130 lucent technologies inc. 12 timing characteristics for 2.7 v operation (continued) * w = number of wait-states. figure 68. external memory data write timing diagram table 162. timing characteristics for external memory data write (all enables) abbreviated reference parameter 20 ns 12.5 ns unit min max min max t131 write overlap (enable low to 3-state) 0 0 ns t132 rwn advance (rwn high to enable high) 0 0 ns t133 rwn delay (enable low to rwn low) 00ns t134 write data setup (data valid to rwn high) t(1 + w)/2 C 4 t(1 + w)/2 C 3 ns t135 rwn width (low to high) t(1 + w) C 5 t(1 + w) C 4 ns t136 write address setup (address valid to rwn low) 00ns eramlo erom cko ab rwn db write address read address v oh v ol v oh v ol v oh v ol v oh v ol v oh v ol write data read w* = 1 t131 t132 t134 t133 t135 t136 (mwait = 0x1002) w* = 2 v oh v ol 5-4022 (f).a
data sheet march 2000 dsp1627 digital signal processor lucent technologies inc. 131 12 timing characteristics for 2.7 v operation (continued) * w = number of wait-states. figure 69. write cycle followed by read cycle table 163. timing characteristics for write cycle followed by read cycle abbreviated reference parameter min max unit t131 write overlap (enable low to 3-state) 0 ns t137 write data 3-state (rwn high to 3-state) 2 ns t138 write data hold (rwn high to data hold) 0 ns t139 write address hold (rwn high to address hold) 0 ns 5-4023 (f).a eramlo cko ab rwn write address read address v oh v ol v oh v ol v oh v ol v oh v ol w* = 1 t137 (mwait = 0x1002) w* = 2 erom v oh v ol db write read v oh v ol t138 t139 t131
data sheet dsp1627 digital signal processor march 2000 132 lucent technologies inc. 12 timing characteristics for 2.7 v operation (continued) 12.8 phif specifications for the phif, "read" means read by the external user (output by the dsp); "write" is similarly defined. the 8-bit reads/ writes are identical to one-half of a 16-bit access. figure 70. phif intel mode signaling (read and write) timing diagram * this timing diagram for the phif port shows accesses using the pcsn signal to initiate and complete a transaction. the transac tions can also be initiated and completed with the pids and pods signals. an output transaction (read) is initiated by pcsn or pods going low, wh ichever comes last. for example, the timing requirements referenced to pcsn going low, t45 and t49, should be referenced to pods going low, i f pods goes low after pcsn. an output transaction is completed by pcsn or pods going high, whichever comes first. an input transaction is i nitiated by pcsn or pids going low, whichever comes last. an input transaction is completed by pcsn or pids going high, whichever comes first. a ll requirements referenced to pcsn apply to pids or pods, if pids or pods is the controlling signal. * this timing diagram for the phif port shows accesses using the pcsn signal to initiate and complete a transaction. the transac tions can also be initiated and completed with the pids and pods signals. an output transaction (read) is initiated by pcsn or pods going low, wh ichever comes last. for example, the timing requirements referenced to pcsn going low, t45 and t49, should be referenced to pods going low, i f pods goes low after pcsn. an output transaction is completed by pcsn or pods going high, whichever comes first. an input transaction is i nitiated by pcsn or pids going low, whichever comes last. an input transaction is completed by pcsn or pids going high, whichever comes first. a ll requirements referenced to pcsn apply to pids or pods, if pids or pods is the controlling signal. table 164. timing requirements for phif intel mode signaling abbreviated reference parameter min max unit t41 pods to pcsn setup (low to low) 0 ns t42 pcsn to pods hold (high to high) 0 ns t43 pids to pcsn setup (low to low) 0 ns t44 pcsn to pids hold (high to high) 0 ns t45* pstat to pcsn setup (valid to low) 6 ns t46* pcsn to pstat hold (high to invalid) 0 ns t47* pbsel to pcsn setup (valid to low) 6 ns t48* pcsn to pbsel hold (high to invalid) 0 ns t51* pb write to pcsn setup (valid to high) 10 ns t52* pcsn to pb write hold (high to invalid) 5 ns table 165. timing characteristics for phif intel mode signaling abbreviated reference parameter min max unit t49* pcsn to pb read (low to valid) 17 ns t50* pcsn to pb read hold (high to invalid) 3 ns 5-4036 (f) pcsn t41 t42 t43 t45 t46 t49 t50 16-bit read 16-bit write pods pids pbsel pstat pb[7:0] t47 t51 t52 t48 t44 t154 v ihC v ilC v ihC v ilC v ihC v ilC v ihC v ilC v ihC v ilC v ihC v ilC
data sheet march 2000 dsp1627 digital signal processor lucent technologies inc. 133 12 timing characteristics for 2.7 v operation (continued) figure 71. phif intel mode signaling (pulse period and flags) timing diagram * t53 should be referenced to the rising edge of pcsn or pods, whichever comes first. t54 should be referenced to the rising edge of pcsn or pids, whichever comes first. ? pobe and pibf may be programmed to be the opposite logic levels shown in the diagram (positive assertion levels shown). t53 an d t54 apply to the inverted levels as well as those shown. table 166. timing requirements for phif intel mode signaling abbreviated reference parameter min max unit t55 pcsn/pods/pids pulse width (high to low) 20.5 ns t56 pcsn/pods/pids pulse width (low to high) 20.5 ns table 167. timing characteristics for phif intel mode signaling abbreviated reference parameter min max unit t53* pcsn/pods to pobe ? (high to high) 20ns t54* pcsn/pids to pibf ? (high to high) 20ns pods pids v ih v il v ih v il v ih v il t55 t56 t55 t56 t55 t56 pcsn t53 t54 16-bit read 8-bit write pbsel pobe pibf t54 v oh v ol v oh v ol v oh v ol t56 t56 t55 t53 8-bit read 16-bit write 5-4037 (f).a
data sheet dsp1627 digital signal processor march 2000 134 lucent technologies inc. 12 timing characteristics for 2.7 v operation (continued) figure 72. phif motorola mode signaling (read and write) timing diagram * this timing diagram for the phif port shows accesses using the pcsn signal to initiate and complete a transaction. the transac tions can also be initiated and completed with the pds signal. an input/output transaction is initiated by pcsn or pds going low, whichev er comes last. for example, the timing requirements referenced to pcsn going low, t45 and t49, should be referenced to pds going low, if pds g oes low after pcsn. an input/output transaction is completed by pcsn or pds going high, whichever comes first. all requirements referen ced to pcsn should be referenced to pds, if pds is the controlling signal. prwn should never be used to initiate or complete a transac tion. ? pds is programmable to be active-high or active-low. it is shown active-low in figures 72 and 73. pobe and pibf may be program med to be the opposite logic levels shown in the diagram. t53 and t54 apply to the inverted levels as well as those shown. * this timing diagram for the phif port shows accesses using the pcsn signal to initiate and complete a transaction. the transac tions can also be initiated and completed with the pds signal. an input/output transaction is initiated by pcsn or pds going low, whichev er comes last. for example, the timing requirements referenced to pcsn going low, t45 and t49, should be referenced to pds going low, if pds g oes low after pcsn. an input/output transaction is completed by pcsn or pds going high, whichever comes first. all requirements referen ced to pcsn should be referenced to pds, if pds is the controlling signal. prwn should never be used to initiate or complete a transac tion. table 168. timing requirements for phif motorola mode signaling abbreviated reference parameter min max unit t41 pds ? to pcsn setup (valid to low) 0ns t42 pcsn to pds ? hold (high to invalid) 0ns t43 prwn to pcsn setup (valid to low) 6 ns t44 pcsn to prwn hold (high to invalid) 0 ns t45* pstat to pcsn setup (valid to low) 6 ns t46* pcsn to pstat hold (high to invalid) 0 ns t47* pbsel to pcsn setup (valid to low) 6 ns t48* pcsn to pbsel hold (high to invalid) 0 ns t51* pb write to pcsn setup (valid to high) 10 ns t52* pcsn to pb write hold (high to invalid) 5 ns table 169. timing characteristics for phif motorola mode signaling abbreviated reference parameter min max unit t49* pcsn to pb read (low to valid) 17 ns t50* pcsn to pb read (high to invalid) 3 ns pcsn pds prwn pbsel pstat pb[7:0] t41 t42 t43 t44 t45 t46 t47 t48 t52 t51 t50 t49 16-bit read 16-bit write t43 t44 v ih v il v ih v il v ih v il v ih v il v ih v il 5-4038 (f).a t154
data sheet march 2000 dsp1627 digital signal processor lucent technologies inc. 135 12 timing characteristics for 2.7 v operation (continued) figure 73. phif motorola mode signaling (pulse period and flags) timing diagram * an input/output transaction is initiated by pcsn or pds going low, whichever comes last. for example, t53 and t54 should be r eferenced to pds going low, if pds goes low after pcsn. an input/output transaction is completed by pcsn or pds going high, whichever comes first. all requirements referenced to pcsn should be referenced to pds, if pds is the controlling signal. prwn should never be used to initiate or complete a transaction. ? pds is programmable to be active-high or active-low. it is shown active-low in figures 72 and 73. pobe and pibf may be program med to be the opposite logic levels shown in the diagram. t53 and t54 apply to the inverted levels as well as those shown. table 170. timing characteristics for phif motorola mode signaling abbreviated reference parameter min max unit t53* pcsn/pds ? to pobe ? (high to high) 20ns t54* pcsn/pds ? to pibf ? (high to high) 20ns table 171. timing requirements for phif motorola mode signaling abbreviated reference parameter min max unit t55 pcsn/pds/prwn pulse width (high to low) 20 ns t56 pcsn/pds/prwn pulse width (low to high) 20 ns pds prwn v ih C t55 t56 t55 t56 t55 t56 pcsn t53 t54 16-bit read 8-bit write pbsel pobe pibf t54 t56 t56 t55 t53 8-bit read 16-bit write v il C v ih C v il C v ih C v il C v oh C v ol C v oh C v ol C v oh C v ol C 5-4039 (f).a
data sheet dsp1627 digital signal processor march 2000 136 lucent technologies inc. 12 timing characteristics for 2.7 v operation (continued) * motorola mode signal name. figure 74. phif intel or motorola mode signaling (status register read) timing diagram ? t45, t47, and t49 are referenced to the falling edge of pcsn or pods(pds), whichever occurs last. ? t46, t48, and t50 are referenced to the rising edge of pcsn or pods(pds), whichever occurs first. ? t45, t47, and t49 are referenced to the falling edge of pcsn or pods(pds), whichever occurs last. ? t46, t48, and t50 are referenced to the rising edge of pcsn or pods(pds), whichever occurs first. table 172. timing requirements for intel and motorola mode signaling (status register read) abbreviated reference parameter min max unit t45 ? pstat to pcsn setup (valid to low) 6 ns t46 ? pcsn to pstat hold (high to invalid) 0 ns t475 ? pbsel to pcsn setup (valid to low) 6 ns t48 ? pcsn to pbsel hold (high to invalid) 0 ns table 173. timing characteristics for intel and motorola mode signaling (status register read) abbreviated reference parameter min max unit t49 ? pcsn to pb read (low to valid) 17 ns t50 ? pcsn to pb read hold (high to invalid) 3 ns pcsn pods (pds*) pids (prwn*) pbsel pstat pb[7:0] t47 t48 t45 t46 t49 t50 v ih v il v oh v ol v ih v il v ih v il v ih v il v ih v il 5-4040 (f).a t154
data sheet march 2000 dsp1627 digital signal processor lucent technologies inc. 137 12 timing characteristics for 2.7 v operation (continued) figure 75. phif, pibf, and pobe reset timing diagram ? pobe and pibf can be programmed to be active-high or active-low. they are shown active-high. the timing characteristic for act ive-low is the same as for active-high. figure 76. phif, pibf, and pobe disable timing diagram * pobe and pibf can be programmed to be active-high or active-low. they are shown active-high. the timing characteristic for act ive-low is the same as for active-high. table 174. phif timing characteristics for phif, pibf, and pobe reset abbreviated reference parameter min max unit t57 rstb disable to pobe/pibf * (high to valid) * after reset, pobe and pibf always go to the levels shown, indicating output buffer empty and input buffer empty. the dsp progr am, however, may later invert the definition of the logic levels for pobe and pibf. t57 and t58 continue to apply. 25 ns t58 rstb enable to pobe/pibf* (low to invalid) 3 25 ns table 175. phif timing characteristics for pobe and pibf disable abbreviated reference parameter min max unit t59 cko to pobe/pibf disable (high/low to disable) 20 ns rstb v ih C t58 t57 v il C pobe v oh C v ol C pibf v oh C v ol C 5-4775 (f) cko v ih C v il C t59 t59 pobe ? v oh C v ol C pibf ? v oh C v ol C 5-4776 (f)
data sheet dsp1627 digital signal processor march 2000 138 lucent technologies inc. 12 timing characteristics for 2.7 v operation (continued) 12.9 serial i/o specifications * n = 16 or 8 bits. figure 77. sio passive mode input timing diagram ? device is fully static; t70 is tested at 200 ns. ? for multiprocessor mode, see note in section 12.10. table 176. timing requirements for serial inputs abbreviated reference parameter min max unit t70 clock period (high to high) ? 40 ? ns t71 clock low time (low to high) 18 ns t72 clock high time (high to low) 18 ns t73 load high setup (high to high) 8 ns t74 load low setup (low to high) 8 ns t75 load high hold (high to invalid) 0 ns t77 data setup (valid to high) 7 ns t78 data hold (high to invalid) 0 ns table 177. timing characteristics for serial outputs abbreviated reference parameter min max unit t79 ibf delay (high to high) 35 ns ibf v oh C v ol C di v ih C v il C ild v ih C v il C ick v ih C v il C bn C 1* b0 t77 t78 b0 b1 t79 t72 t71 t70 t75 t74 t75 t73 5-4777 (f)
data sheet march 2000 dsp1627 digital signal processor lucent technologies inc. 139 12 timing characteristics for 2.7 v operation (continued) * ild goes high during bit 6 (of 0:15), n = 8 or 16. figure 78. sio active mode input timing diagram table 178. timing requirements for serial inputs abbreviated reference parameter min max unit t77 data setup (valid to high) 7 ns t78 data hold (high to invalid) 0 ns table 179. timing characteristics for serial outputs abbreviated reference parameter min max unit t76a ild delay (high to low) 35 ns t101 ild hold (high to invalid) 5 ns t79 ibf delay (high to high) 35 ns ibf v oh C v ol C di v ih C v il C ild v oh C v ol C ick v oh C v ol C bn C 1 b0 t77 t78 b0 b1 t79 t101 t76a * 5-4778 (f)
data sheet dsp1627 digital signal processor march 2000 140 lucent technologies inc. 12 timing characteristics for 2.7 v operation (continued) * see sioc register, msb field, to determine if b0 is the msb or lsb. see sioc register, ilen field, to determine if the do word length is 8 bits or 16 bits. figure 79. sio passive mode output timing diagram ? device is fully static; t80 is tested at 200 ns. ? for multiprocessor mode, see note in section 12.10. table 180. timing requirements for serial inputs abbreviated reference parameter min max unit t80 clock period (high to high) ? 40 ? ns t81 clock low time (low to high) 18 ns t82 clock high time (high to low) 18 ns t83 load high setup (high to high) 8 ns t84 load low setup (low to high) 8 ns t85 load hold (high to invalid) 0 ns table 181. timing characteristics for serial outputs abbreviated reference parameter min max unit t87 data delay (high to valid) 35 ns t88 enable data delay (low to active) 35 ns t89 disable data delay (high to 3-state) 35 ns t90 data hold (high to invalid) 5 ns t92 address delay (high to valid) 35 ns t93 address hold (high to invalid) 5 ns t94 enable delay (low to active) 35 ns t95 disable delay (high to 3-state) 35 ns t96 obe delay (high to high) 35 ns doen v ih C v il C sadd v oh C v ol C old v ih C v il C ock v ih C v il C t85 t80 t81 t82 t84 t83 t85 t88 b0 b1 b7 bn C 1 t90 t90 t87 t94 ad0 ad1 ad7 t93 t93 t92 as7 t89 t95 obe v oh C v ol C do* v oh C v ol C t96 5-4796 (f)
data sheet march 2000 dsp1627 digital signal processor lucent technologies inc. 141 12 timing characteristics for 2.7 v operation (continued) * old goes high at the end of bit 6 of 0:15. figure 80. sio active mode output timing diagram table 182. timing characteristics for serial output abbreviated reference parameter min max unit t86a old delay (high to low) 35 ns t102 old hold (high to invalid) 5 ns t87 data delay (high to valid) 35 ns t88 enable data delay (low to active) 35 ns t89 disable data delay (high to 3-state) 35 ns t90 data hold (high to invalid) 5 ns t92 address delay (high to valid) 35 ns t93 address hold (high to invalid) 5 ns t94 enable delay (low to active) 35 ns t95 disable delay (high to 3-state) 35 ns t96 obe delay (high to high) 35 ns 5-4797 (f) doen v ih C v il C sadd v oh C v ol C old v oh C v ol C ock v oh C v ol C t102 t86a t88 b0 b1 b7 bn C 1 t90 t90 t87 t94 ad0 ad1 ad7 t93 t93 t92 as7 t89 t95 obe v oh C v ol C do v oh C v ol C t96 *
data sheet dsp1627 digital signal processor march 2000 142 lucent technologies inc. 12 timing characteristics for 2.7 v operation (continued) * see sioc register, ld field. figure 81. serial i/o active mode clock timing table 183. timing characteristics for signal generation abbreviated reference parameter min max unit t97 ick delay (high to high) 18 ns t98 ick delay (high to low) 18 ns t99 ock delay (high to high) 18 ns t100 ock delay (high to low) 18 ns t76a ild delay (high to low) 35 ns t76b ild delay (high to high) 35 ns t101 ild hold (high to invalid) 5 ns t86a old delay (high to low) 35 ns t86b old delay (high to high) 35 ns t102 old hold (high to invalid) 5 ns t103 sync delay (high to low) 35 ns t104 sync delay (high to high) 35 ns t105 sync hold (high to invalid) 5 ns ick v oh C v ol C cko v oh C v ol C t97 ock v oh C v ol C ick/ock* v oh C ild v oh C v ol C old v oh C v ol C sync v oh C v ol C t99 t98 t100 t101 t76a t101 t76b t102 t86a t102 t86b t105 t103 t105 t104 5-4798 (f)
data sheet march 2000 dsp1627 digital signal processor lucent technologies inc. 143 12 timing characteristics for 2.7 v operation (continued) 12.10 multiprocessor communication * negative edge initiates time slot 0. figure 82. sio multiprocessor timing diagram note: all serial i/o timing requirements and characteristics still apply, but the minimum clock period in passive multiprocessor mode, assuming 50% duty cycle, is calculated as (t77 + t116) x 2. * with capacitance load on ick, ock, do, sync, and sadd = 100 pf, add 4 ns to t116t122. table 184. timing requirements for sio multiprocessor communication abbreviated reference parameter min max unit t112 sync setup (high/low to high) 35 ns t113 sync hold (high to high/low) 0 ns t114 address setup (valid to high) 12 ns t115 address hold (high to invalid) 0 ns table 185. timing characteristics for sio multiprocessor communication abbreviated reference* parameter min max unit t116 data delay (bit 0 only) (low to valid) 35 ns t117 data disable delay (high to 3-state) 30 ns t120 doen valid delay (high to valid) 25 ns t121 address delay (bit 0 only) (low to valid) 35 ns t122 address disable delay (high to 3-state) 30 ns ock/ick b0 b15 b8 b7 b1 b0 b15 sync v ih C v il C do/d1 v oh C v ol C doen v oh C v ol C t112 t113 t112 t113 time slot 1 time slot 2 t117 t116 ad0 as7 as0 ad7 ad1 ad0 sadd t122 t121 t114 t115 t120 t120 * 5-4799 (f)
data sheet dsp1627 digital signal processor march 2000 144 lucent technologies inc. 13 crystal electrical characteristics and requirements if the option for using the external crystal is chosen, the following electrical characteristics and requirements apply. 13.1 external components for the crystal oscillator the crystal oscillator is enabled by connecting a crystal across cki and cki2, along with one external capacitor from each of these pins to ground (see figure 83). for most applications, 10 pf external capacitors are recommended; however, larger values allow for better frequency precision (see section 13.4, frequency accuracy considerations). the crystal should be either fundamental or overtone mode, parallel resonant, with a rated power (drive level) of at least 1 mw, and specified at a load capacitance equal to the total capacitance seen by the crystal (including external capacitors and strays). the series resistance of the crystal should be specified to be less than half the absolute value of the negative resistance shown in figure 84 or figure 85 for the crystal frequency. the frequency of the signal at the cki input pin is equal to the crystal frequency. figure 83. fundamental crystal configuration the following guidelines should be followed when designing the printed-circuit board layout for a crystal-based ap- plication: 1. keep crystal and external capacitors as close to cki and cki2 pins as possible to minimize board stray capaci- tance. 2. keep high-frequency digital signals such as cko away from cki and cki2 traces to avoid coupling. 13.2 power dissipation figures 86 and 87 indicate the typical power dissipation of the on-chip crystal oscillator circuit versus frequency. note that these curves are intended to show the relative effects of load capacitance on supply current and that the actual supply current measured depends on crystal resistance. for typical crystals, measured supply current at the v dda pin should be less than that shown in the figures. 5-4041 (f).a cki cki2 xtal c 1 c 2
data sheet march 2000 dsp1627 digital signal processor lucent technologies inc. 145 13 crystal electrical characteristics and requirements (continued) figure 84. negative resistance of crystal oscillator circuit, v dd = 4.75 v figure 85. negative resistance of crystal oscillator circuit, v dd = 2.7 v cki cki2 c 1 c 2 c 0 z( w ) c 1 = c 2 = c ext c 0 = parasitic capacitance of crystal (7 pf maximum) 5-3529 (f).b 0 C40 C80 C120 C160 C200 0 5 10 15 20 25 40 frequency (mhz) re [z] ( w ) 30 35 C240 C280 C320 C360 C400 C440 C480 C520 C560 C600 C640 C680 C720 C760 C800 c 1 , c 2 = 10 pf c 1 , c 2 = 50 pf c 1 , c 2 = 20 pf 5-3527 (f).b 0 C40 C80 C120 C160 C200 0 5 10 15 20 25 40 frequency (mhz) re {z} ( w ) 30 35 C240 C280 C320 C360 C400 C440 C480 C520 C560 C600 C640 C680 C720 C760 C800 c 1 , c 2 = 20 pf c 1 , c 2 = 10 pf c 1 , c 2 = 50 pf
data sheet dsp1627 digital signal processor march 2000 146 lucent technologies inc. 13 crystal electrical characteristics and requirements (continued) figure 86. typical supply current of crystal oscillator circuit, v dd = 5.0 v, 25 c figure 87. typical supply current of crystal oscillator circuit, v dd = 2.7 v, 25 c 5-5188 (f) 6.5 6.0 5.5 5.0 4.5 3.0 2 8 14 18 22 26 30 34 38 frequency (mhz) average oscillator current (ma) 4.0 3.5 4 1216202428323640 10 6 7.0 c 1 = c 2 = 10 pf c 1 = c 2 = 50 pf 5-5189 (f) 1.5 0.0 2 8 14 18 22 26 30 frequency (mhz) average oscillator current (ma) 1.0 0.5 4 1216202428 10 6 2.0 0 c 1 = c 2 = 10 pf c 1 = c 2 = 50 pf
data sheet march 2000 dsp1627 digital signal processor lucent technologies inc. 147 13 crystal electrical characteristics and requirements (continued) 13.3 lc network design for third overtone crystal circuits for certain crystal applications, it is cheaper to use a third overtone crystal instead of a fundamental mode crystal. when using third overtone crystals, it is necessary, however, to filter out the fundamental frequency so that the cir- cuit will oscillate only at the third overtone. there are several techniques that will accomplish this; one of these is described below. figure 88 shows the basic setup for third overtone operation. figure 88. third overtone crystal configuration the parallel combination of l 1 and c 1 forms a resonant circuit with a resonant frequency between the first and third harmonic of the crystal such that the lc network appears inductive at the fundamental frequency and capacitive at the third harmonic. this ensures that a 360 phase shift around the oscillator loop will occur at the third overtone frequency but not at the fundamental. the blocking capacitor, c 3 , provides dc isolation for the trap circuit and should be chosen to be large compared to c 1 . for example, suppose it is desired to operate with a 40 mhz, third overtone, crystal: let: f 3 = operating frequency of third overtone crystal (40 mhz in this example) f 1 = fundamental frequency of third overtone crystal, or f 3 /3 (13.3 mhz in this example) f t = resonant frequency of trap = c 2 = external load capacitor (10 pf in this example) c 3 = dc blocking capacitor (0.1 m f in this example) arbitrarily, set trap resonance to geometric mean of f 1 and f 3 . since f 1 = f 3 /3, the geometric mean would be: 5-4043 (f).a cki cki2 xtal c 1 c 2 c 3 l 1 1 2 p l 1 c 1 ------------------------- - f t f 3 3 ------- 40 mhz 3 -------------------- 2 3 m h z = = =
data sheet dsp1627 digital signal processor march 2000 148 lucent technologies inc. 13 crystal electrical characteristics and requirements (continued) at the third overtone frequency, f 3 , it is desirable to have the net impedance of the trap circuit (x t ) equal to the im- pedance of c 2 (x c2 ), i.e., selecting c 3 so that x c3 << x l1 yields, for a capacitor, for an inductor, solving for c 1 , and realizing that l 1 c 1 = 3/ w 3 2 yields, hence, for c 2 = 10 pf, c 1 = 15 pf. since the impedance of the trap circuit in this example would be equal to the impedance of a 10 pf capacitor, the negative resistance and supply current curves for c 1 = c 2 = 10 pf at 40 mhz would apply to this example. finally, solving for the inductor value, for the above example, l 1 is 3.2 m h. x t x c2 x c1 x c3 x l1 + () || == x t x c2 x c1 x l1 || == x c j C w c -------- w h e r e w 2 p f = = x l j w l = c 1 3 2 -- - c 2 = l 1 1 4 p 2 f t 2 c 1 -------------------------- - =
data sheet march 2000 dsp1627 digital signal processor lucent technologies inc. 149 13 crystal electrical characteristics and requirements (continued) 13.4 frequency accuracy considerations for frequency accuracy implications of using the pll, see section 4.12, clock synthesis. for most applications, clock frequency errors in the hundreds of parts per million can be tolerated with no adverse effects. however, for applications where precise average frequency tolerance on the order of 100 ppm is required, care must be taken in the choice of external components (crystal and capacitors) as well as in the layout of the printed-circuit board. several factors determine the frequency accuracy of a crystal-based oscillator circuit. some of these factors are determined by the properties of the crystal itself. generally, a low-cost, standard crystal will not be sufficient for a high-accuracy application, and a custom crystal must be specified. most crystal manufacturers provide extensive information concerning the accuracy of their crystals, and an applications engineer from the crystal vendor should be consulted prior to specifying a crystal for a given application. in addition to absolute, temperature, and aging tolerances of a crystal, the operating frequency of a crystal is also de- termined by the total load capacitance seen by the crystal. when ordering a crystal from a vendor, it is necessary to specify a load capacitance at which the operating frequency of the crystal will be measured. variations in this load capacitance due to temperature and manufacturing variations will cause variations in the operating frequency of the oscillator. figure 89 illustrates some of the sources of this variation. notes: c ext = external load capacitor (one each required for cki and cki2). c d = parasitic capacitance of the dsp1627 itself. c b = parasitic capacitance of the printed-wiring board. c o = parasitic capacitance of crystal (not part of c l , but still a source of frequency variation). figure 89. components of load capacitance for crystal oscillator the load capacitance, cl, must be specified to the crystal vendor. the crystal manufacturer will cut the crystal so that the frequency of oscillation will be correct when the crystal sees this load capacitance. note that c l refers to a capacitance seen across the crystal leads, meaning that for the circuit shown in figure 89, c l is the series combi- nation of the two external capacitors (c ext /2) plus the equivalent board and device strays (c b /2 + c d /2). for exam- ple, if 10 pf external capacitors were used and parasitic capacitance is neglected, then the crystal should be specified for a load capacitance of 5 pf. if the load capacitance deviates from this value due to the tolerance on the external capacitors or the presence of strays, then the frequency will also deviate. this change in frequency as func- tion of load capacitance is known as pullability and is expressed in units of ppm/pf. for small deviations of a few pf, pullability can be determined by the equation below: where c 0 = parasitic capacitance of crystal in pf. c 1 = motional capacitance of crystal in pf (usually between 1 ff to 25 ff, value available from crystal vendor). c l = total load capacitance in pf seen by crystal. 5-4045 (f).a cki cki2 xtal c d c b c ext c d c b c ext c l c o pullability (ppm/pf) c 1 () 10 6 () 2 c 0 c l + () 2 -------------------------------- =
data sheet dsp1627 digital signal processor march 2000 150 lucent technologies inc. 13 crystal electrical characteristics and requirements (continued) note that for a given crystal, the pullability can be reduced, and, hence, the frequency stability improved, by making cl as large as possible while still maintaining sufficient negative resistance to ensure start-up per the curves shown in figures 86 and 87. since it is not possible to know the exact values of the parasitic capacitance in a crystal-based oscillator system, the external capacitors are usually selected empirically to null out the frequency offset on a typical prototype board. thus, if a crystal is specified to operate with a load capacitance of 10 pf, the external capacitors would have to be made slightly less than 20 pf each in order to account for strays. suppose, for instance, that a crystal for which c l = 10 pf is specified is plugged into the system and it is determined empirical that the best frequency accuracy occurs with cext = 18 pf. this would mean that the equivalent board and device strays from each leac to ground would be 2 pf. as an example, suppose it is desired to design a 23 mhz, 3.3 v system with 100 ppm frequency accuracy. the parameters for a typical high-accuracy, custom, 23 mhz fundamental mode crystal are as follows: initial tolerance 10 ppm temperature tolerance 25 ppm aging tolerance 6 ppm series resistance 20 w max. motional capacitance (c 1 ) 15 ff max. parasitic capacitance (c 0 ) 7 pf max. in order to ensure oscillator start-up, the negative resistance of the oscillator with load and parasitic capacitance must be at least twice the series resistance of the crystal, or 40 w . interpolating from figure 89, external capacitors plus strays can be made as large as 30 pf while still achieving 40 w of negative resistance. assume for this example that external capacitors are chosen so that the total load capacitance including strays is 30 pf per lead, or 15 pf total. thus, a load capacitance, c l = 15 pf would be specified to the crystal manufacturer. from the above equation, the pullability would be calculated as follows: if 2% external capacitors are used, the frequency deviation due to capacitor tolerance is equal to: (0.02)(15 pf)(15.5 ppm/pf) = 4.7 ppm note: to simplify analysis, c ext is considered to be 30 pf. in practice, it would be slightly less than this value to account for strays. also, temperature and aging tolerances on the capacitors have been neglected. typical capacitance variation of the oscillator circuit in the dsp1627 itself across process, temperature, and supply voltage is 1 pf. thus, the expected frequency variation due to the dsp1627 is: (1 pf)(15.5 ppm/pf) = 15.5 ppm approximate variation in parasitic capacitance of crystal = 0.5 pf. frequency shift due to variation in c 0 = (0.5 pf)(15.5 ppm/pf) = 7.75 ppm approximate variation in parasitic capacitance of printed-circuit board = 1.5 pf. frequency shift due to variation in board capacitance = (1.5 pf)(15.5 ppm/pf) = 23.25 ppm pullability c 1 () 10 6 () 2c 0 c l + () 2 -------------------------------- 0.015 () 10 6 () 27 15 + () 2 ---------------------------------- 1 5 . 5 p p m / p f == =
data sheet march 2000 dsp1627 digital signal processor lucent technologies inc. 151 13 crystal electrical characteristics and requirements (continued) thus, the contributions to frequency variation add up as follows: initial tolerance of crystal 10.0 ppm temperature tolerance of crystal 25.0 aging tolerance of crystal 6.0 load capacitor variation 4.7 dsp1627 circuit variation1 5.5 c 0 variation 7.8 board variation 23.3 total 92.3 ppm this type of detailed analysis should be performed for any crystal-based application where frequency accuracy is critical.
data sheet dsp1627 digital signal processor march 2000 152 lucent technologies inc. 14 outline diagrams 14.1 100-pin bqfp (bumpered quad flat pack) all dimensions are in millimeters. 5-1970 (f)r.10 pin #1 identifier zone 89 1 13 14 38 39 6 3 64 88 19.050 0.405 22.350 0.255 22.860 0.305 22.350 0.255 19.050 0.405 22.860 0.305 edge chamfer detail a 4.570 max detail b 0.760 0.255 0.635 typ 0.10 seating plane 3.555 0.255 detail b 0.280 0.075 0.150 m 0.175 0.025 detail a 0.255 0.91/1.17 gage plane seating plane
data sheet march 2000 dsp1627 digital signal processor lucent technologies inc. 153 14 outline diagrams (continued) 14.2 100-pin tqfp (thin quad flat pack) all dimensions are in millimeters. 0.50 typ 1.60 max seating plane 0.08 1.40 0.05 0.05/0.15 detail a detail b 14.00 0.20 16.00 0.20 76 100 1 25 26 50 51 75 14.00 0.20 16.00 0.20 pin #1 identifier zone detail b 0.19/0.27 0.08 m 0.106/0.200 detail a 0.45/0.75 gage plane seating plane 1.00 ref 0.25 5-2146 (f)r.14
lucent technologies inc. reserves the right to make changes to the product(s) or information contained herein without notice. n o liability is assumed as a result of their use or application. no rights under any patent accompany the sale of any such product(s) or information. copyright ? 2000 lucent technologies inc. all rights reserved march 2000 ds00-205wtec (replaces ds00-061wtec) for additional information, contact your microelectronics group account manager or the following: internet: http://www.lucent.com/micro e-mail: docmaster@micro.lucent.com n. america: microelectronics group, lucent technologies inc., 555 union boulevard, room 30l-15p-ba, allentown, pa 18103 1-800-372-2447 , fax 610-712-4106 (in canada: 1-800-553-2448 , fax 610-712-4106) asia pacific: microelectronics group, lucent technologies singapore pte. ltd., 77 science park drive, #03-18 cintech iii, singap ore 118256 tel. (65) 778 8833 , fax (65) 777 7495 china: microelectronics group, lucent technologies (china) co., ltd., a-f2, 23/f, zao fong universe building, 1800 zhong shan xi road, shanghai 200233 p. r. china tel. (86) 21 6440 0468 , ext. 316 , fax (86) 21 6440 0652 japan: microelectronics group, lucent technologies japan ltd., 7-18, higashi-gotanda 2-chome, shinagawa-ku, tokyo 141, japan tel. (81) 3 5421 1600 , fax (81) 3 5421 1700 europe: data requests: microelectronics group dataline: tel. (44) 7000 582 368 , fax (44) 1189 328 148 technical inquiries:germany: (49) 89 95086 0 (munich), united kingdom: (44) 1344 865 900 (ascot), france: (33) 1 40 83 68 00 (paris), sweden: (46) 8 594 607 00 (stockholm), finland: (358) 9 4354 2800 (helsinki), italy: (39) 02 6608131 (milan), spain: (34) 1 807 1441 (madrid)

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